bfin.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

;; PIC, movsi is responsible for determining when the source address
;; needs PIC relocation and appropriately calling legitimize_pic_address
;; to perform the actual relocation.

(define_expand "movsi"
  [(set (match_operand:SI 0 "nonimmediate_operand" "")
	(match_operand:SI 1 "general_operand" ""))]
  ""
  "expand_move (operands, SImode);")

(define_expand "movv2hi"
  [(set (match_operand:V2HI 0 "nonimmediate_operand" "")
	(match_operand:V2HI 1 "general_operand" ""))]
  ""
  "expand_move (operands, V2HImode);")

(define_expand "movdi"
  [(set (match_operand:DI 0 "nonimmediate_operand" "")
	(match_operand:DI 1 "general_operand" ""))]
  ""
  "expand_move (operands, DImode);")

(define_expand "movsf"
 [(set (match_operand:SF 0 "nonimmediate_operand" "")
       (match_operand:SF 1 "general_operand" ""))]
  ""
  "expand_move (operands, SFmode);")

(define_expand "movdf"
 [(set (match_operand:DF 0 "nonimmediate_operand" "")
       (match_operand:DF 1 "general_operand" ""))]
  ""
  "expand_move (operands, DFmode);")

(define_expand "movhi"
  [(set (match_operand:HI 0 "nonimmediate_operand" "")
	(match_operand:HI 1 "general_operand" ""))]
  ""
  "expand_move (operands, HImode);")

(define_expand "movqi"
  [(set (match_operand:QI 0 "nonimmediate_operand" "")
	(match_operand:QI 1 "general_operand" ""))]
  ""
  " expand_move (operands, QImode); ")

;; Some define_splits to break up SI/SFmode loads of immediate constants.

(define_split
  [(set (match_operand:SI 0 "validreg_operand" "")
	(match_operand:SI 1 "symbolic_or_const_operand" ""))]
  "reload_completed
   /* Always split symbolic operands; split integer constants that are
      too large for a single instruction.  */
   && (GET_CODE (operands[1]) != CONST_INT
       || (INTVAL (operands[1]) < -32768
 	   || INTVAL (operands[1]) >= 65536
	   || (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))"
  [(set (match_dup 0) (high:SI (match_dup 1)))
   (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))]
{
  if (GET_CODE (operands[1]) == CONST_INT
      && split_load_immediate (operands))
    DONE;
  /* ??? Do something about TARGET_LOW_64K.  */
})

(define_split
  [(set (match_operand:SF 0 "validreg_operand" "")
	(match_operand:SF 1 "immediate_operand" ""))]
  "reload_completed"
  [(set (match_dup 2) (high:SI (match_dup 3)))
   (set (match_dup 2) (lo_sum:SI (match_dup 2) (match_dup 3)))]
{
  long values;
  REAL_VALUE_TYPE value;

  if (GET_CODE (operands[1]) != CONST_DOUBLE)
    abort ();

  REAL_VALUE_FROM_CONST_DOUBLE (value, operands[1]);
  REAL_VALUE_TO_TARGET_SINGLE (value, values);

  operands[2] = gen_rtx_REG (SImode, true_regnum (operands[0]));
  operands[3] = GEN_INT (trunc_int_for_mode (values, SImode));
  if (values >= -32768 && values < 65536)
    {
      emit_move_insn (operands[2], operands[3]);
      DONE;
    }
  if (split_load_immediate (operands + 2))
    DONE;
})

;; Sadly, this can't be a proper named movstrict pattern, since the compiler
;; expects to be able to use registers for operand 1.
;; Note that the asm instruction is defined by the manual to take an unsigned
;; constant, but it doesn't matter to the assembler, and the compiler only
;; deals with sign-extended constants.  Hence "Ksh".
(define_insn "*movstricthi"
  [(set (strict_low_part (match_operand:HI 0 "validreg_operand" "+x"))
	(match_operand:HI 1 "immediate_operand" "Ksh"))]
  ""
  "%h0 = %1;"
  [(set_attr "type" "mvi")
   (set_attr "length" "4")])

;; Sign and zero extensions

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "validreg_operand" "=d, d")
	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
  ""
  "@
   %0 = %h1 (X);
   %0 = W %h1 (X);"
  [(set_attr "type" "alu0,mcld")])

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "validreg_operand" "=d, d")
	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d, m")))]
  ""
  "@
   %0 = %h1 (Z);
   %0 = W%h1 (Z);"
  [(set_attr "type" "alu0,mcld")])

(define_insn "zero_extendbisi2"
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(zero_extend:SI (match_operand:BI 1 "nonimmediate_operand" "C")))]
  ""
  "%0 = %1;"
  [(set_attr "type" "compare")])

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "validreg_operand" "=d, d")
	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
  ""
  "@
   %0 = B %1 (X);
   %0 = %T1 (X);"
  [(set_attr "type" "mcld,alu0")])

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "validreg_operand" "=d, d")
	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
  ""
  "@
   %0 = B %1 (X);
   %0 = %T1 (X);"
  [(set_attr "type" "mcld,alu0")])


(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "validreg_operand" "=d, d")
	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
  ""
  "@
   %0 = B %1 (Z);
   %0 = %T1 (Z);"
  [(set_attr "type" "mcld,alu0")])


(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "validreg_operand" "=d, d")
	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m, d")))]
  ""
  "@
   %0 = B %1 (Z);
   %0 = %T1 (Z);"
  [(set_attr "type" "mcld,alu0")])

;; DImode logical operations

(define_code_macro any_logical [and ior xor])
(define_code_attr optab [(and "and")
			 (ior "ior")
			 (xor "xor")])
(define_code_attr op [(and "&")
		      (ior "|")
		      (xor "^")])
(define_code_attr high_result [(and "0")
			       (ior "%H1")
			       (xor "%H1")])

(define_insn "<optab>di3"
  [(set (match_operand:DI 0 "validreg_operand" "=d")
        (any_logical:DI (match_operand:DI 1 "validreg_operand" "0")
			(match_operand:DI 2 "validreg_operand" "d")))]
  ""
  "%0 = %1 <op> %2;\\n\\t%H0 = %H1 <op> %H2;"
  [(set_attr "length" "4")])

(define_insn "*<optab>di_zesidi_di"
  [(set (match_operand:DI 0 "validreg_operand" "=d")
        (any_logical:DI (zero_extend:DI
			 (match_operand:SI 2 "validreg_operand" "d"))
			(match_operand:DI 1 "validreg_operand" "d")))]
  ""
  "%0 = %1 <op>  %2;\\n\\t%H0 = <high_result>;"
  [(set_attr "length" "4")])

(define_insn "*<optab>di_sesdi_di"
  [(set (match_operand:DI 0 "validreg_operand" "=d")
        (any_logical:DI (sign_extend:DI
			 (match_operand:SI 2 "validreg_operand" "d"))
			(match_operand:DI 1 "validreg_operand" "0")))
   (clobber (match_scratch:SI 3 "=&d"))]
  ""
  "%0 = %1 <op> %2;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 <op> %3;"
  [(set_attr "length" "8")])

(define_insn "negdi2"
  [(set (match_operand:DI 0 "validreg_operand" "=d")
        (neg:DI (match_operand:DI 1 "validreg_operand" "d")))
   (clobber (match_scratch:SI 2 "=&d"))
   (clobber (reg:CC REG_CC))]
  ""
  "%2 = 0; %2 = %2 - %1; cc = ac0; cc = !cc; %2 = cc;\\n\\t%0 = -%1; %H0 = -%H1; %H0 = %H0 - %2;"
  [(set_attr "length" "16")])

(define_insn "one_cmpldi2"
  [(set (match_operand:DI 0 "validreg_operand" "=d")
        (not:DI (match_operand:DI 1 "validreg_operand" "d")))]
  ""
  "%0 = ~%1;\\n\\t%H0 = ~%H1;"
  [(set_attr "length" "4")])

;; DImode zero and sign extend patterns

(define_insn_and_split "zero_extendsidi2"
  [(set (match_operand:DI 0 "validreg_operand" "=d")
        (zero_extend:DI (match_operand:SI 1 "validreg_operand" "d")))]
  ""
  "#"
  "reload_completed"
  [(set (match_dup 3) (const_int 0))]
{
  split_di (operands, 1, operands + 2, operands + 3);
  if (REGNO (operands[0]) != REGNO (operands[1]))
    emit_move_insn (operands[2], operands[1]);
})

(define_insn "zero_extendqidi2"
  [(set (match_operand:DI 0 "validreg_operand" "=d")
        (zero_extend:DI (match_operand:QI 1 "validreg_operand" "d")))]
  ""
  "%0 = %T1 (Z);\\n\\t%H0 = 0;"
  [(set_attr "length" "4")])

(define_insn "zero_extendhidi2"
  [(set (match_operand:DI 0 "validreg_operand" "=d")
        (zero_extend:DI (match_operand:HI 1 "validreg_operand" "d")))]
  ""
  "%0 = %h1 (Z);\\n\\t%H0 = 0;"
  [(set_attr "length" "4")])

(define_insn_and_split "extendsidi2"
  [(set (match_operand:DI 0 "validreg_operand" "=d")
        (sign_extend:DI (match_operand:SI 1 "validreg_operand" "d")))]
  ""
  "#"
  "reload_completed"
  [(set (match_dup 3) (match_dup 1))
   (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
{
  split_di (operands, 1, operands + 2, operands + 3);
  if (REGNO (operands[0]) != REGNO (operands[1]))
    emit_move_insn (operands[2], operands[1]);
})

(define_insn_and_split "extendqidi2"
  [(set (match_operand:DI 0 "validreg_operand" "=d")
        (sign_extend:DI (match_operand:QI 1 "validreg_operand" "d")))]
  ""
  "#"
  "reload_completed"
  [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
   (set (match_dup 3) (sign_extend:SI (match_dup 1)))
   (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
{
  split_di (operands, 1, operands + 2, operands + 3);
})

(define_insn_and_split "extendhidi2"
  [(set (match_operand:DI 0 "validreg_operand" "=d")
        (sign_extend:DI (match_operand:HI 1 "validreg_operand" "d")))]
  ""
  "#"
  "reload_completed"
  [(set (match_dup 2) (sign_extend:SI (match_dup 1)))
   (set (match_dup 3) (sign_extend:SI (match_dup 1)))
   (set (match_dup 3) (ashiftrt:SI (match_dup 3) (const_int 31)))]
{
  split_di (operands, 1, operands + 2, operands + 3);
})

;; DImode arithmetic operations

(define_insn "adddi3"
  [(set (match_operand:DI 0 "validreg_operand" "=&d,&d,&d")
        (plus:DI (match_operand:DI 1 "validreg_operand" "%0,0,0")
                 (match_operand:DI 2 "nonmemory_operand" "Kn7,Ks7,d")))
   (clobber (match_scratch:SI 3 "=&d,&d,&d"))
   (clobber (reg:CC 34))]
  ""
  "@
   %0 += %2; cc = ac0; %3 = cc; %H0 += -1; %H0 = %H0 + %3;
   %0 += %2; cc = ac0; %3 = cc; %H0 = %H0 + %3;
   %0 = %0 + %2; cc = ac0; %3 = cc; %H0 = %H0 + %H2; %H0 = %H0 + %3;"
  [(set_attr "type" "alu0")
   (set_attr "length" "10,8,10")])

(define_insn "subdi3"
  [(set (match_operand:DI 0 "validreg_operand" "=&d")
        (minus:DI (match_operand:DI 1 "validreg_operand" "0")
                  (match_operand:DI 2 "validreg_operand" "d")))
   (clobber (reg:CC 34))]
  ""
  "%0 = %1-%2;\\n\\tcc = ac0;\\n\\t%H0 = %H1-%H2;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
  [(set_attr "length" "10")])

(define_insn "*subdi_di_zesidi"
  [(set (match_operand:DI 0 "validreg_operand" "=d")
        (minus:DI (match_operand:DI 1 "validreg_operand" "0")
                  (zero_extend:DI
                  (match_operand:SI 2 "validreg_operand" "d"))))
   (clobber (match_scratch:SI 3 "=&d"))
   (clobber (reg:CC 34))]
  ""
  "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%H0 = %H1 - %3;"
  [(set_attr "length" "10")])

(define_insn "*subdi_zesidi_di"
  [(set (match_operand:DI 0 "validreg_operand" "=d")
        (minus:DI (zero_extend:DI
                  (match_operand:SI 2 "validreg_operand" "d"))
                  (match_operand:DI 1 "validreg_operand" "0")))
   (clobber (match_scratch:SI 3 "=&d"))
   (clobber (reg:CC 34))]
  ""
  "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\tcc = ! cc;\\n\\t%3 = cc;\\n\\t%3 = -%3;\\n\\t%H0 = %3 - %H1"
  [(set_attr "length" "12")])

(define_insn "*subdi_di_sesidi"
  [(set (match_operand:DI 0 "validreg_operand" "=d")
        (minus:DI (match_operand:DI 1 "validreg_operand" "0")
                  (sign_extend:DI
                  (match_operand:SI 2 "validreg_operand" "d"))))
   (clobber (match_scratch:SI 3 "=&d"))
   (clobber (reg:CC 34))]
  ""
  "%0 = %1 - %2;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %H1 - %3;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
  [(set_attr "length" "14")])

(define_insn "*subdi_sesidi_di"
  [(set (match_operand:DI 0 "validreg_operand" "=d")
        (minus:DI (sign_extend:DI
                  (match_operand:SI 2 "validreg_operand" "d"))
                  (match_operand:DI 1 "validreg_operand" "0")))
   (clobber (match_scratch:SI 3 "=&d"))
   (clobber (reg:CC 34))]
  ""
  "%0 = %2 - %1;\\n\\tcc = ac0;\\n\\t%3 = %2;\\n\\t%3 >>>= 31;\\n\\t%H0 = %3 - %H1;\\n\\tif cc jump 1f;\\n\\t%H0 += -1;\\n\\t1:"
  [(set_attr "length" "14")])

;; Combined shift/add instructions

(define_insn ""
  [(set (match_operand:SI 0 "validreg_operand" "=a,d")
	(ashift:SI (plus:SI (match_operand:SI 1 "validreg_operand" "%0,0")
		            (match_operand:SI 2 "validreg_operand" "a,d"))
		   (match_operand:SI 3 "pos_scale_operand" "P1P2,P1P2")))]
  ""
  "%0 = (%0 + %2) << %3;" /* "shadd %0,%2,%3;" */
  [(set_attr "type" "alu0")])

(define_insn ""
  [(set (match_operand:SI 0 "validreg_operand" "=a")
	(plus:SI (match_operand:SI 1 "validreg_operand" "a")
		 (mult:SI (match_operand:SI 2 "validreg_operand" "a")
			  (match_operand:SI 3 "scale_by_operand" "i"))))]
  ""
  "%0 = %1 + (%2 << %X3);"
  [(set_attr "type" "alu0")])

(define_insn ""
  [(set (match_operand:SI 0 "validreg_operand" "=a")
	(plus:SI (match_operand:SI 1 "validreg_operand" "a")
		 (ashift:SI (match_operand:SI 2 "validreg_operand" "a")
			    (match_operand:SI 3 "pos_scale_operand" "i"))))]
  ""
  "%0 = %1 + (%2 << %3);"
  [(set_attr "type" "alu0")])

(define_insn ""
  [(set (match_operand:SI 0 "validreg_operand" "=a")
	(plus:SI (mult:SI (match_operand:SI 1 "validreg_operand" "a")
			  (match_operand:SI 2 "scale_by_operand" "i"))
		 (match_operand:SI 3 "validreg_operand" "a")))]
  ""
  "%0 = %3 + (%1 << %X2);"
  [(set_attr "type" "alu0")])

(define_insn ""
  [(set (match_operand:SI 0 "validreg_operand" "=a")
	(plus:SI (ashift:SI (match_operand:SI 1 "validreg_operand" "a")
			    (match_operand:SI 2 "pos_scale_operand" "i"))
		 (match_operand:SI 3 "validreg_operand" "a")))]
  ""
  "%0 = %3 + (%1 << %2);"
  [(set_attr "type" "alu0")])

(define_insn "mulhisi3"
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(mult:SI (sign_extend:SI (match_operand:HI 1 "validreg_operand" "%d"))
		 (sign_extend:SI (match_operand:HI 2 "validreg_operand" "d"))))]
  ""
  "%0 = %h1 * %h2 (IS);"
  [(set_attr "type" "dsp32")])

(define_insn "umulhisi3"
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(mult:SI (zero_extend:SI (match_operand:HI 1 "validreg_operand" "%d"))
		 (zero_extend:SI (match_operand:HI 2 "validreg_operand" "d"))))]
  ""
  "%0 = %h1 * %h2 (FU);"
  [(set_attr "type" "dsp32")])

;; The processor also supports ireg += mreg or ireg -= mreg, but these
;; are unusable if we don't ensure that the corresponding lreg is zero.
;; The same applies to the add/subtract constant versions involving
;; iregs

(define_insn "addsi3"
  [(set (match_operand:SI 0 "validreg_operand" "=ad,a,d")
	(plus:SI (match_operand:SI 1 "validreg_operand" "%0, a,d")
		 (match_operand:SI 2 "reg_or_7bit_operand" "Ks7, a,d")))]
  ""
  "@
   %0 += %2;
   %0 = %1 + %2;
   %0 = %1 + %2;"
  [(set_attr "type" "alu0")
   (set_attr "length" "2,2,2")])

(define_expand "subsi3"
  [(set (match_operand:SI 0 "validreg_operand" "")
	(minus:SI (match_operand:SI 1 "validreg_operand" "")
		  (match_operand:SI 2 "reg_or_7bit_operand" "")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:SI 0 "validreg_operand" "=da,d,a")
	(minus:SI (match_operand:SI 1 "validreg_operand" "0,d,0")
		  (match_operand:SI 2 "reg_or_7bit_operand" "Ks7,d,a")))]
  "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -64"
{
  static const char *const strings_subsi3[] = {
    "%0 += -%2;",
    "%0 = %1 - %2;",
    "%0 -= %2;",
  };

  if (CONSTANT_P (operands[2]) && INTVAL (operands[2]) < 0) {
     rtx tmp_op = operands[2];
     operands[2] = GEN_INT (-INTVAL (operands[2]));
     output_asm_insn ("%0 += %2;", operands);
     operands[2] = tmp_op;
     return "";
  }

  return strings_subsi3[which_alternative];
}
  [(set_attr "type" "alu0")])