arm.h

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

  {"abort-on-noreturn",         ARM_FLAG_ABORT_NORETURN,		\
   N_("Generate a call to abort if a noreturn function returns")},	\
  {"no-abort-on-noreturn",     -ARM_FLAG_ABORT_NORETURN, "" },		\
  {"no-sched-prolog",           ARM_FLAG_NO_SCHED_PRO,			\
   N_("Do not move instructions into a function's prologue") },		\
  {"sched-prolog",             -ARM_FLAG_NO_SCHED_PRO, "" },		\
  {"single-pic-base",		ARM_FLAG_SINGLE_PIC_BASE,		\
   N_("Do not load the PIC register in function prologues") },		\
  {"no-single-pic-base",       -ARM_FLAG_SINGLE_PIC_BASE, "" },		\
  {"long-calls",		ARM_FLAG_LONG_CALLS,			\
   N_("Generate call insns as indirect calls, if necessary") },		\
  {"no-long-calls",	       -ARM_FLAG_LONG_CALLS, "" },		\
  {"thumb",                     ARM_FLAG_THUMB,				\
   N_("Compile for the Thumb not the ARM") },				\
  {"no-thumb",                 -ARM_FLAG_THUMB, "" },			\
  {"arm",                      -ARM_FLAG_THUMB, "" },			\
  {"tpcs-frame",		    THUMB_FLAG_BACKTRACE,		\
   N_("Thumb: Generate (non-leaf) stack frames even if not needed") },	   \
  {"no-tpcs-frame",                -THUMB_FLAG_BACKTRACE, "" },		   \
  {"tpcs-leaf-frame",	  	    THUMB_FLAG_LEAF_BACKTRACE,		   \
   N_("Thumb: Generate (leaf) stack frames even if not needed") },	   \
  {"no-tpcs-leaf-frame",           -THUMB_FLAG_LEAF_BACKTRACE, "" },	   \
  {"callee-super-interworking",	    THUMB_FLAG_CALLEE_SUPER_INTERWORKING,  \
   N_("Thumb: Assume non-static functions may be called from ARM code") }, \
  {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING,  \
     "" },								   \
  {"caller-super-interworking",	    THUMB_FLAG_CALLER_SUPER_INTERWORKING,  \
   N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
  {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING,  \
   "" },								   \
  {"cirrus-fix-invalid-insns",      CIRRUS_FIX_INVALID_INSNS,		   \
   N_("Cirrus: Place NOPs to avoid invalid instruction combinations") },   \
  {"no-cirrus-fix-invalid-insns",  -CIRRUS_FIX_INVALID_INSNS,		   \
   N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\
  SUBTARGET_SWITCHES							   \
  {"",				TARGET_DEFAULT, "" }			   \
}

#define TARGET_OPTIONS							\
{									\
  {"cpu=",  & arm_select[0].string,					\
   N_("Specify the name of the target CPU"), 0},			\
  {"arch=", & arm_select[1].string,					\
   N_("Specify the name of the target architecture"), 0},		\
  {"tune=", & arm_select[2].string, "", 0},				\
  {"fpe=",  & target_fpe_name, "", 0},					\
  {"fp=",  & target_fpe_name, "", 0},					\
  {"fpu=",  & target_fpu_name,						\
   N_("Specify the name of the target floating point hardware/format"), 0}, \
  {"float-abi=", & target_float_abi_name,				\
   N_("Specify if floating point hardware should be used"), 0},		\
  {"structure-size-boundary=", & structure_size_string,			\
   N_("Specify the minimum bit alignment of structures"), 0},		\
  {"pic-register=", & arm_pic_register_string,				\
   N_("Specify the register to be used for PIC addressing"), 0},	\
  {"abi=", &target_abi_name, N_("Specify an ABI"), 0},			\
  {"soft-float", &target_float_switch,					\
   N_("Alias for -mfloat-abi=soft"), "s"},				\
  {"hard-float", &target_float_switch,					\
   N_("Alias for -mfloat-abi=hard"), "h"}				\
}

/* Support for a compile-time default CPU, et cetera.  The rules are:
   --with-arch is ignored if -march or -mcpu are specified.
   --with-cpu is ignored if -march or -mcpu are specified, and is overridden
    by --with-arch.
   --with-tune is ignored if -mtune or -mcpu are specified (but not affected
     by -march).
   --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
   specified.
   --with-fpu is ignored if -mfpu is specified.
   --with-abi is ignored is -mabi is specified.  */
#define OPTION_DEFAULT_SPECS \
  {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
  {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
  {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
  {"float", \
    "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
  {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
  {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},

struct arm_cpu_select
{
  const char *              string;
  const char *              name;
  const struct processors * processors;
};

/* This is a magic array.  If the user specifies a command line switch
   which matches one of the entries in TARGET_OPTIONS then the corresponding
   string pointer will be set to the value specified by the user.  */
extern struct arm_cpu_select arm_select[];

/* Which floating point model to use.  */
enum arm_fp_model
{
  ARM_FP_MODEL_UNKNOWN,
  /* FPA model (Hardware or software).  */
  ARM_FP_MODEL_FPA,
  /* Cirrus Maverick floating point model.  */
  ARM_FP_MODEL_MAVERICK,
  /* VFP floating point model.  */
  ARM_FP_MODEL_VFP
};

extern enum arm_fp_model arm_fp_model;

/* Which floating point hardware is available.  Also update
   fp_model_for_fpu in arm.c when adding entries to this list.  */
enum fputype
{
  /* No FP hardware.  */
  FPUTYPE_NONE,
  /* Full FPA support.  */
  FPUTYPE_FPA,
  /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM).  */
  FPUTYPE_FPA_EMU2,
  /* Emulated FPA hardware, Issue 3 emulator.  */
  FPUTYPE_FPA_EMU3,
  /* Cirrus Maverick floating point co-processor.  */
  FPUTYPE_MAVERICK,
  /* VFP.  */
  FPUTYPE_VFP
};

/* Recast the floating point class to be the floating point attribute.  */
#define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)

/* What type of floating point to tune for */
extern enum fputype arm_fpu_tune;

/* What type of floating point instructions are available */
extern enum fputype arm_fpu_arch;

enum float_abi_type
{
  ARM_FLOAT_ABI_SOFT,
  ARM_FLOAT_ABI_SOFTFP,
  ARM_FLOAT_ABI_HARD
};

extern enum float_abi_type arm_float_abi;

#ifndef TARGET_DEFAULT_FLOAT_ABI
#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
#endif

/* Which ABI to use.  */
enum arm_abi_type
{
  ARM_ABI_APCS,
  ARM_ABI_ATPCS,
  ARM_ABI_AAPCS,
  ARM_ABI_IWMMXT
};

extern enum arm_abi_type arm_abi;

#ifndef ARM_DEFAULT_ABI
#define ARM_DEFAULT_ABI ARM_ABI_APCS
#endif

/* Nonzero if this chip supports the ARM Architecture 3M extensions.  */
extern int arm_arch3m;

/* Nonzero if this chip supports the ARM Architecture 4 extensions.  */
extern int arm_arch4;

/* Nonzero if this chip supports the ARM Architecture 4T extensions.  */
extern int arm_arch4t;

/* Nonzero if this chip supports the ARM Architecture 5 extensions.  */
extern int arm_arch5;

/* Nonzero if this chip supports the ARM Architecture 5E extensions.  */
extern int arm_arch5e;

/* Nonzero if this chip supports the ARM Architecture 6 extensions.  */
extern int arm_arch6;

/* Nonzero if this chip can benefit from load scheduling.  */
extern int arm_ld_sched;

/* Nonzero if generating thumb code.  */
extern int thumb_code;

/* Nonzero if this chip is a StrongARM.  */
extern int arm_is_strong;

/* Nonzero if this chip is a Cirrus variant.  */
extern int arm_arch_cirrus;

/* Nonzero if this chip supports Intel XScale with Wireless MMX technology.  */
extern int arm_arch_iwmmxt;

/* Nonzero if this chip is an XScale.  */
extern int arm_arch_xscale;

/* Nonzero if tuning for XScale  */
extern int arm_tune_xscale;

/* Nonzero if this chip is an ARM6 or an ARM7.  */
extern int arm_is_6_or_7;

/* Nonzero if we should define __THUMB_INTERWORK__ in the
   preprocessor.
   XXX This is a bit of a hack, it's intended to help work around
   problems in GLD which doesn't understand that armv5t code is
   interworking clean.  */
extern int arm_cpp_interwork;

#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT  (ARM_FLAG_APCS_FRAME)
#endif

/* The frame pointer register used in gcc has nothing to do with debugging;
   that is controlled by the APCS-FRAME option.  */
#define CAN_DEBUG_WITHOUT_FP

#define OVERRIDE_OPTIONS  arm_override_options ()

/* Nonzero if PIC code requires explicit qualifiers to generate
   PLT and GOT relocs rather than the assembler doing so implicitly.
   Subtargets can override these if required.  */
#ifndef NEED_GOT_RELOC
#define NEED_GOT_RELOC	0
#endif
#ifndef NEED_PLT_RELOC
#define NEED_PLT_RELOC	0
#endif

/* Nonzero if we need to refer to the GOT with a PC-relative
   offset.  In other words, generate

   .word	_GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]

   rather than

   .word	_GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)

   The default is true, which matches NetBSD.  Subtargets can
   override this if required.  */
#ifndef GOT_PCREL
#define GOT_PCREL   1
#endif

/* Target machine storage Layout.  */


/* Define this macro if it is advisable to hold scalars in registers
   in a wider mode than that declared by the program.  In such cases,
   the value is constrained to be within the bounds of the declared
   type, but kept valid in the wider mode.  The signedness of the
   extension may differ from that of the type.  */

/* It is far faster to zero extend chars than to sign extend them */

#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
  if (GET_MODE_CLASS (MODE) == MODE_INT		\
      && GET_MODE_SIZE (MODE) < 4)      	\
    {						\
      if (MODE == QImode)			\
	UNSIGNEDP = 1;				\
      else if (MODE == HImode)			\
	UNSIGNEDP = 1;				\
      (MODE) = SImode;				\
    }

#define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE)	\
  if (GET_MODE_CLASS (MODE) == MODE_INT		\
      && GET_MODE_SIZE (MODE) < 4)      	\
    (MODE) = SImode;				\

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.  */
#define BITS_BIG_ENDIAN  0

/* Define this if most significant byte of a word is the lowest numbered.
   Most ARM processors are run in little endian mode, so that is the default.
   If you want to have it run-time selectable, change the definition in a
   cover file to be TARGET_BIG_ENDIAN.  */
#define BYTES_BIG_ENDIAN  (TARGET_BIG_END != 0)

/* Define this if most significant word of a multiword number is the lowest
   numbered.
   This is always false, even when in big-endian mode.  */
#define WORDS_BIG_ENDIAN  (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)

/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
   on processor pre-defineds when compiling libgcc2.c.  */
#if defined(__ARMEB__) && !defined(__ARMWEL__)
#define LIBGCC2_WORDS_BIG_ENDIAN 1
#else
#define LIBGCC2_WORDS_BIG_ENDIAN 0
#endif

/* Define this if most significant word of doubles is the lowest numbered.
   The rules are different based on whether or not we use FPA-format,
   VFP-format or some other floating point co-processor's format doubles.  */
#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())

#define UNITS_PER_WORD	4

/* True if natural alignment is used for doubleword types.  */
#define ARM_DOUBLEWORD_ALIGN	TARGET_AAPCS_BASED

#define DOUBLEWORD_ALIGNMENT 64

#define PARM_BOUNDARY  	32

#define STACK_BOUNDARY  (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)

#define PREFERRED_STACK_BOUNDARY \
    (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)

#define FUNCTION_BOUNDARY  32

/* The lowest bit is used to indicate Thumb-mode functions, so the
   vbit must go into the delta field of pointers to member
   functions.  */
#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta

#define EMPTY_FIELD_BOUNDARY  32

#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)

/* XXX Blah -- this macro is used directly by libobjc.  Since it
   supports no vector modes, cut out the complexity and fall back
   on BIGGEST_FIELD_ALIGNMENT.  */
#ifdef IN_TARGET_LIBS
#define BIGGEST_FIELD_ALIGNMENT 64
#endif

/* Make strings word-aligned so strcpy from constants will be faster.  */
#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)

#define CONSTANT_ALIGNMENT(EXP, ALIGN)				\
   ((TREE_CODE (EXP) == STRING_CST				\
     && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR)	\
    ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))