📄 arm.h
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/* Definitions of target machine for GNU compiler, for ARM. Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). More major hacks by Richard Earnshaw (rearnsha@arm.com) Minor hacks by Nick Clifton (nickc@cygnus.com) This file is part of GCC. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GCC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */#ifndef GCC_ARM_H#define GCC_ARM_H/* The architecture define. */extern char arm_arch_name[];/* Target CPU builtins. */#define TARGET_CPU_CPP_BUILTINS() \ do \ { \ /* Define __arm__ even when in thumb mode, for \ consistency with armcc. */ \ builtin_define ("__arm__"); \ builtin_define ("__APCS_32__"); \ if (TARGET_THUMB) \ builtin_define ("__thumb__"); \ \ if (TARGET_BIG_END) \ { \ builtin_define ("__ARMEB__"); \ if (TARGET_THUMB) \ builtin_define ("__THUMBEB__"); \ if (TARGET_LITTLE_WORDS) \ builtin_define ("__ARMWEL__"); \ } \ else \ { \ builtin_define ("__ARMEL__"); \ if (TARGET_THUMB) \ builtin_define ("__THUMBEL__"); \ } \ \ if (TARGET_SOFT_FLOAT) \ builtin_define ("__SOFTFP__"); \ \ if (TARGET_VFP) \ builtin_define ("__VFP_FP__"); \ \ /* Add a define for interworking. \ Needed when building libgcc.a. */ \ if (arm_cpp_interwork) \ builtin_define ("__THUMB_INTERWORK__"); \ \ builtin_assert ("cpu=arm"); \ builtin_assert ("machine=arm"); \ \ builtin_define (arm_arch_name); \ if (arm_arch_cirrus) \ builtin_define ("__MAVERICK__"); \ if (arm_arch_xscale) \ builtin_define ("__XSCALE__"); \ if (arm_arch_iwmmxt) \ builtin_define ("__IWMMXT__"); \ if (TARGET_AAPCS_BASED) \ builtin_define ("__ARM_EABI__"); \ } while (0)/* The various ARM cores. */enum processor_type{#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ IDENT,#include "arm-cores.def"#undef ARM_CORE /* Used to indicate that no processor has been specified. */ arm_none};enum target_cpus{#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ TARGET_CPU_##IDENT,#include "arm-cores.def"#undef ARM_CORE TARGET_CPU_generic};/* The processor for which instructions should be scheduled. */extern enum processor_type arm_tune;typedef enum arm_cond_code{ ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV}arm_cc;extern arm_cc arm_current_cc;#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))extern int arm_target_label;extern int arm_ccfsm_state;extern GTY(()) rtx arm_target_insn;/* Run-time compilation parameters selecting different hardware subsets. */extern int target_flags;/* The floating point mode. */extern const char *target_fpu_name;/* For backwards compatibility. */extern const char *target_fpe_name;/* Whether to use floating point hardware. */extern const char *target_float_abi_name;/* For -m{soft,hard}-float. */extern const char *target_float_switch;/* Which ABI to use. */extern const char *target_abi_name;/* Define the information needed to generate branch insns. This is stored from the compare operation. */extern GTY(()) rtx arm_compare_op0;extern GTY(()) rtx arm_compare_op1;/* The label of the current constant pool. */extern rtx pool_vector_label;/* Set to 1 when a return insn is output, this means that the epilogue is not needed. */extern int return_used_this_function;/* Used to produce AOF syntax assembler. */extern GTY(()) rtx aof_pic_label; /* Just in case configure has failed to define anything. */#ifndef TARGET_CPU_DEFAULT#define TARGET_CPU_DEFAULT TARGET_CPU_generic#endif#undef CPP_SPEC#define CPP_SPEC "%(subtarget_cpp_spec) \%{msoft-float:%{mhard-float: \ %e-msoft-float and -mhard_float may not be used together}} \%{mbig-endian:%{mlittle-endian: \ %e-mbig-endian and -mlittle-endian may not be used together}}"#ifndef CC1_SPEC#define CC1_SPEC ""#endif/* This macro defines names of additional specifications to put in the specs that can be used in various specifications like CC1_SPEC. Its definition is an initializer with a subgrouping for each command option. Each subgrouping contains a string constant, that defines the specification name, and a string constant that used by the GCC driver program. Do not define this macro if it does not need to do anything. */#define EXTRA_SPECS \ { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ SUBTARGET_EXTRA_SPECS#ifndef SUBTARGET_EXTRA_SPECS#define SUBTARGET_EXTRA_SPECS#endif#ifndef SUBTARGET_CPP_SPEC#define SUBTARGET_CPP_SPEC ""#endif /* Run-time Target Specification. */#ifndef TARGET_VERSION#define TARGET_VERSION fputs (" (ARM/generic)", stderr);#endif/* Nonzero if the function prologue (and epilogue) should obey the ARM Procedure Call Standard. */#define ARM_FLAG_APCS_FRAME (1 << 0)/* Nonzero if the function prologue should output the function name to enable the post mortem debugger to print a backtrace (very useful on RISCOS, unused on RISCiX). Specifying this flag also enables -fno-omit-frame-pointer. XXX Must still be implemented in the prologue. */#define ARM_FLAG_POKE (1 << 1)/* Nonzero if floating point instructions are emulated by the FPE, in which case instruction scheduling becomes very uninteresting. */#define ARM_FLAG_FPE (1 << 2)/* FLAG 0x0008 now spare (used to be apcs-32 selection). *//* Nonzero if stack checking should be performed on entry to each function which allocates temporary variables on the stack. */#define ARM_FLAG_APCS_STACK (1 << 4)/* Nonzero if floating point parameters should be passed to functions in floating point registers. */#define ARM_FLAG_APCS_FLOAT (1 << 5)/* Nonzero if re-entrant, position independent code should be generated. This is equivalent to -fpic. */#define ARM_FLAG_APCS_REENT (1 << 6) /* FLAG 0x0080 now spare (used to be alignment traps). */ /* FLAG (1 << 8) is now spare (used to be soft-float). *//* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */#define ARM_FLAG_BIG_END (1 << 9)/* Nonzero if we should compile for Thumb interworking. */#define ARM_FLAG_INTERWORK (1 << 10)/* Nonzero if we should have little-endian words even when compiling for big-endian (for backwards compatibility with older versions of GCC). */#define ARM_FLAG_LITTLE_WORDS (1 << 11)/* Nonzero if we need to protect the prolog from scheduling */#define ARM_FLAG_NO_SCHED_PRO (1 << 12)/* Nonzero if a call to abort should be generated if a noreturn function tries to return. */#define ARM_FLAG_ABORT_NORETURN (1 << 13)/* Nonzero if function prologues should not load the PIC register. */#define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)/* Nonzero if all call instructions should be indirect. */#define ARM_FLAG_LONG_CALLS (1 << 15)/* Nonzero means that the target ISA is the THUMB, not the ARM. */#define ARM_FLAG_THUMB (1 << 16)/* Set if a TPCS style stack frame should be generated, for non-leaf functions, even if they do not need one. */#define THUMB_FLAG_BACKTRACE (1 << 17)/* Set if a TPCS style stack frame should be generated, for leaf functions, even if they do not need one. */#define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)/* Set if externally visible functions should assume that they might be called in ARM mode, from a non-thumb aware code. */#define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)/* Set if calls via function pointers should assume that their destination is non-Thumb aware. */#define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)/* Fix invalid Cirrus instruction combinations by inserting NOPs. */#define CIRRUS_FIX_INVALID_INSNS (1 << 21)#define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)#define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)#define TARGET_FPE (target_flags & ARM_FLAG_FPE)#define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)#define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)#define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)/* Use hardware floating point instructions. */#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)/* Use hardware floating point calling convention. */#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)#define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)#define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)#define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)#define TARGET_IWMMXT (arm_arch_iwmmxt)#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)#define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)#define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)#define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)#define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)#define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)#define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)#define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)#define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)#define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)#define TARGET_ARM (! TARGET_THUMB)#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */#define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)#define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)#define TARGET_BACKTRACE (leaf_function_p () \ ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \ : (target_flags & THUMB_FLAG_BACKTRACE))#define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS)#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)#define TARGET_AAPCS_BASED \ (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)/* True iff the full BPABI is being used. If TARGET_BPABI is true, then TARGET_AAPCS_BASED must be true -- but the converse does not hold. TARGET_BPABI implies the use of the BPABI runtime library, etc., in addition to just the AAPCS calling conventions. */#ifndef TARGET_BPABI#define TARGET_BPABI false#endif/* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */#ifndef SUBTARGET_SWITCHES#define SUBTARGET_SWITCHES#endif#define TARGET_SWITCHES \{ \ {"apcs", ARM_FLAG_APCS_FRAME, "" }, \ {"apcs-frame", ARM_FLAG_APCS_FRAME, \ N_("Generate APCS conformant stack frames") }, \ {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \ {"poke-function-name", ARM_FLAG_POKE, \ N_("Store function names in object code") }, \ {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \ {"fpe", ARM_FLAG_FPE, "" }, \ {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \ {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \ {"apcs-float", ARM_FLAG_APCS_FLOAT, \ N_("Pass FP arguments in FP registers") }, \ {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \ {"apcs-reentrant", ARM_FLAG_APCS_REENT, \ N_("Generate re-entrant, PIC code") }, \ {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \ {"big-endian", ARM_FLAG_BIG_END, \ N_("Assume target CPU is configured as big endian") }, \ {"little-endian", -ARM_FLAG_BIG_END, \ N_("Assume target CPU is configured as little endian") }, \ {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \ N_("Assume big endian bytes, little endian words") }, \ {"thumb-interwork", ARM_FLAG_INTERWORK, \ N_("Support calls between Thumb and ARM instruction sets") }, \ {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \⌨️ 快捷键说明
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