iwmmxt.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

		       (match_operand:SI   2 "register_operand" "z")))]
  "TARGET_REALLY_IWMMXT"
  "wsrawg%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashrdi3_iwmmxt"
  [(set (match_operand:DI              0 "register_operand" "=y")
	(ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
		   (match_operand:SI   2 "register_operand" "z")))]
  "TARGET_REALLY_IWMMXT"
  "wsradg%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "lshrv4hi3"
  [(set (match_operand:V4HI                0 "register_operand" "=y")
        (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
		       (match_operand:SI   2 "register_operand" "z")))]
  "TARGET_REALLY_IWMMXT"
  "wsrlhg%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "lshrv2si3"
  [(set (match_operand:V2SI                0 "register_operand" "=y")
        (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
		       (match_operand:SI   2 "register_operand" "z")))]
  "TARGET_REALLY_IWMMXT"
  "wsrlwg%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "lshrdi3_iwmmxt"
  [(set (match_operand:DI              0 "register_operand" "=y")
	(lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
		     (match_operand:SI 2 "register_operand" "z")))]
  "TARGET_REALLY_IWMMXT"
  "wsrldg%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashlv4hi3"
  [(set (match_operand:V4HI              0 "register_operand" "=y")
        (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
		     (match_operand:SI   2 "register_operand" "z")))]
  "TARGET_REALLY_IWMMXT"
  "wsllhg%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashlv2si3"
  [(set (match_operand:V2SI              0 "register_operand" "=y")
        (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
		       (match_operand:SI 2 "register_operand" "z")))]
  "TARGET_REALLY_IWMMXT"
  "wsllwg%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashldi3_iwmmxt"
  [(set (match_operand:DI            0 "register_operand" "=y")
	(ashift:DI (match_operand:DI 1 "register_operand" "y")
		   (match_operand:SI 2 "register_operand" "z")))]
  "TARGET_REALLY_IWMMXT"
  "wslldg%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "rorv4hi3_di"
  [(set (match_operand:V4HI                0 "register_operand" "=y")
        (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
		       (match_operand:DI   2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wrorh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "rorv2si3_di"
  [(set (match_operand:V2SI                0 "register_operand" "=y")
        (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
		       (match_operand:DI   2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wrorw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "rordi3_di"
  [(set (match_operand:DI              0 "register_operand" "=y")
	(rotatert:DI (match_operand:DI 1 "register_operand" "y")
		   (match_operand:DI   2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wrord%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashrv4hi3_di"
  [(set (match_operand:V4HI                0 "register_operand" "=y")
        (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
		       (match_operand:DI   2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsrah%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashrv2si3_di"
  [(set (match_operand:V2SI                0 "register_operand" "=y")
        (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
		       (match_operand:DI   2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsraw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashrdi3_di"
  [(set (match_operand:DI              0 "register_operand" "=y")
	(ashiftrt:DI (match_operand:DI 1 "register_operand" "y")
		   (match_operand:DI   2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsrad%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "lshrv4hi3_di"
  [(set (match_operand:V4HI                0 "register_operand" "=y")
        (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
		       (match_operand:DI   2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsrlh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "lshrv2si3_di"
  [(set (match_operand:V2SI                0 "register_operand" "=y")
        (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")
		       (match_operand:DI   2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsrlw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "lshrdi3_di"
  [(set (match_operand:DI              0 "register_operand" "=y")
	(lshiftrt:DI (match_operand:DI 1 "register_operand" "y")
		     (match_operand:DI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsrld%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashlv4hi3_di"
  [(set (match_operand:V4HI              0 "register_operand" "=y")
        (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y")
		     (match_operand:DI   2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsllh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashlv2si3_di"
  [(set (match_operand:V2SI              0 "register_operand" "=y")
        (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y")
		       (match_operand:DI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsllw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashldi3_di"
  [(set (match_operand:DI            0 "register_operand" "=y")
	(ashift:DI (match_operand:DI 1 "register_operand" "y")
		   (match_operand:DI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wslld%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wmadds"
  [(set (match_operand:V4HI               0 "register_operand" "=y")
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
		      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDS))]
  "TARGET_REALLY_IWMMXT"
  "wmadds%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wmaddu"
  [(set (match_operand:V4HI               0 "register_operand" "=y")
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
		      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDU))]
  "TARGET_REALLY_IWMMXT"
  "wmaddu%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tmia"
  [(set (match_operand:DI                    0 "register_operand" "=y")
	(plus:DI (match_operand:DI           1 "register_operand" "0")
		 (mult:DI (sign_extend:DI
			   (match_operand:SI 2 "register_operand" "r"))
			  (sign_extend:DI
			   (match_operand:SI 3 "register_operand" "r")))))]
  "TARGET_REALLY_IWMMXT"
  "tmia%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tmiaph"
  [(set (match_operand:DI          0 "register_operand" "=y")
	(plus:DI (match_operand:DI 1 "register_operand" "0")
		 (plus:DI
		  (mult:DI (sign_extend:DI
			    (truncate:HI (match_operand:SI 2 "register_operand" "r")))
			   (sign_extend:DI
			    (truncate:HI (match_operand:SI 3 "register_operand" "r"))))
		  (mult:DI (sign_extend:DI
			    (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16))))
			   (sign_extend:DI
			    (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))]
  "TARGET_REALLY_IWMMXT"
  "tmiaph%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tmiabb"
  [(set (match_operand:DI          0 "register_operand" "=y")
	(plus:DI (match_operand:DI 1 "register_operand" "0")
		 (mult:DI (sign_extend:DI
			   (truncate:HI (match_operand:SI 2 "register_operand" "r")))
			  (sign_extend:DI
			   (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
  "TARGET_REALLY_IWMMXT"
  "tmiabb%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tmiatb"
  [(set (match_operand:DI          0 "register_operand" "=y")
	(plus:DI (match_operand:DI 1 "register_operand" "0")
		 (mult:DI (sign_extend:DI
			   (truncate:HI (ashiftrt:SI
					 (match_operand:SI 2 "register_operand" "r")
					 (const_int 16))))
			  (sign_extend:DI
			   (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
  "TARGET_REALLY_IWMMXT"
  "tmiatb%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tmiabt"
  [(set (match_operand:DI          0 "register_operand" "=y")
	(plus:DI (match_operand:DI 1 "register_operand" "0")
		 (mult:DI (sign_extend:DI
			   (truncate:HI (match_operand:SI 2 "register_operand" "r")))
			  (sign_extend:DI
			   (truncate:HI (ashiftrt:SI
					 (match_operand:SI 3 "register_operand" "r")
					 (const_int 16)))))))]
  "TARGET_REALLY_IWMMXT"
  "tmiabt%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tmiatt"
  [(set (match_operand:DI          0 "register_operand" "=y")
	(plus:DI (match_operand:DI 1 "register_operand" "0")
		 (mult:DI (sign_extend:DI
			   (truncate:HI (ashiftrt:SI
					 (match_operand:SI 2 "register_operand" "r")
					 (const_int 16))))
			  (sign_extend:DI
			   (truncate:HI (ashiftrt:SI
					 (match_operand:SI 3 "register_operand" "r")
					 (const_int 16)))))))]
  "TARGET_REALLY_IWMMXT"
  "tmiatt%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tbcstqi"
  [(set (match_operand:V8QI                   0 "register_operand" "=y")
	(vec_duplicate:V8QI (match_operand:QI 1 "register_operand" "r")))]
  "TARGET_REALLY_IWMMXT"
  "tbcstb%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tbcsthi"
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
	(vec_duplicate:V4HI (match_operand:HI 1 "register_operand" "r")))]
  "TARGET_REALLY_IWMMXT"
  "tbcsth%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tbcstsi"
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
	(vec_duplicate:V2SI (match_operand:SI 1 "register_operand" "r")))]
  "TARGET_REALLY_IWMMXT"
  "tbcstw%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tmovmskb"
  [(set (match_operand:SI               0 "register_operand" "=r")
	(unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
  "TARGET_REALLY_IWMMXT"
  "tmovmskb%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tmovmskh"
  [(set (match_operand:SI               0 "register_operand" "=r")
	(unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
  "TARGET_REALLY_IWMMXT"
  "tmovmskh%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tmovmskw"
  [(set (match_operand:SI               0 "register_operand" "=r")
	(unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
  "TARGET_REALLY_IWMMXT"
  "tmovmskw%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_waccb"
  [(set (match_operand:DI               0 "register_operand" "=y")
	(unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))]
  "TARGET_REALLY_IWMMXT"
  "waccb%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wacch"
  [(set (match_operand:DI               0 "register_operand" "=y")
	(unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))]
  "TARGET_REALLY_IWMMXT"
  "wacch%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_waccw"
  [(set (match_operand:DI               0 "register_operand" "=y")
	(unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))]
  "TARGET_REALLY_IWMMXT"
  "waccw%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_walign"
  [(set (match_operand:V8QI                           0 "register_operand" "=y,y")
	(subreg:V8QI (ashiftrt:TI
		      (subreg:TI (vec_concat:V16QI
				  (match_operand:V8QI 1 "register_operand" "y,y")
				  (match_operand:V8QI 2 "register_operand" "y,y")) 0)
		      (mult:SI
		       (match_operand:SI              3 "nonmemory_operand" "i,z")
		       (const_int 8))) 0))]
  "TARGET_REALLY_IWMMXT"
  "@
   waligni%?\\t%0, %1, %2, %3
   walignr%U3%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tmrc"
  [(set (match_operand:SI                      0 "register_operand" "=r")
	(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")]
			    VUNSPEC_TMRC))]
  "TARGET_REALLY_IWMMXT"
  "tmrc%?\\t%0, %w1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tmcr"
  [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
			(match_operand:SI 1 "register_operand"  "r")]
		       VUNSPEC_TMCR)]
  "TARGET_REALLY_IWMMXT"
  "tmcr%?\\t%w0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wsadb"
  [(set (match_operand:V8QI               0 "register_operand" "=y")
        (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
		      (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSAD))]
  "TARGET_REALLY_IWMMXT"
  "wsadb%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wsadh"
  [(set (match_operand:V4HI               0 "register_operand" "=y")
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
		      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSAD))]
  "TARGET_REALLY_IWMMXT"
  "wsadh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wsadbz"
  [(set (match_operand:V8QI               0 "register_operand" "=y")
        (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
		      (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))]
  "TARGET_REALLY_IWMMXT"
  "wsadbz%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wsadhz"
  [(set (match_operand:V4HI               0 "register_operand" "=y")
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
		      (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))]
  "TARGET_REALLY_IWMMXT"
  "wsadhz%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])