iwmmxt.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

  "TARGET_REALLY_IWMMXT"
  "wmaxsw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "umaxv2si3"
  [(set (match_operand:V2SI            0 "register_operand" "=y")
        (umax:V2SI (match_operand:V2SI 1 "register_operand" "y")
		   (match_operand:V2SI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wmaxuw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "sminv8qi3"
  [(set (match_operand:V8QI            0 "register_operand" "=y")
        (smin:V8QI (match_operand:V8QI 1 "register_operand" "y")
		   (match_operand:V8QI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wminsb%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "uminv8qi3"
  [(set (match_operand:V8QI            0 "register_operand" "=y")
        (umin:V8QI (match_operand:V8QI 1 "register_operand" "y")
		   (match_operand:V8QI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wminub%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "sminv4hi3"
  [(set (match_operand:V4HI            0 "register_operand" "=y")
        (smin:V4HI (match_operand:V4HI 1 "register_operand" "y")
		   (match_operand:V4HI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wminsh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "uminv4hi3"
  [(set (match_operand:V4HI            0 "register_operand" "=y")
        (umin:V4HI (match_operand:V4HI 1 "register_operand" "y")
		   (match_operand:V4HI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wminuh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "sminv2si3"
  [(set (match_operand:V2SI            0 "register_operand" "=y")
        (smin:V2SI (match_operand:V2SI 1 "register_operand" "y")
		   (match_operand:V2SI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wminsw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "uminv2si3"
  [(set (match_operand:V2SI            0 "register_operand" "=y")
        (umin:V2SI (match_operand:V2SI 1 "register_operand" "y")
		   (match_operand:V2SI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wminuw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

;; Pack/unpack insns.

(define_insn "iwmmxt_wpackhss"
  [(set (match_operand:V8QI                    0 "register_operand" "=y")
	(vec_concat:V8QI
	 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
	 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
  "TARGET_REALLY_IWMMXT"
  "wpackhss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wpackwss"
  [(set (match_operand:V4HI                    0 "register_operand" "=y")
	(vec_concat:V4HI
	 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
	 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
  "TARGET_REALLY_IWMMXT"
  "wpackwss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wpackdss"
  [(set (match_operand:V2SI                0 "register_operand" "=y")
	(vec_concat:V2SI
	 (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
	 (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
  "TARGET_REALLY_IWMMXT"
  "wpackdss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wpackhus"
  [(set (match_operand:V8QI                    0 "register_operand" "=y")
	(vec_concat:V8QI
	 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
	 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
  "TARGET_REALLY_IWMMXT"
  "wpackhus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wpackwus"
  [(set (match_operand:V4HI                    0 "register_operand" "=y")
	(vec_concat:V4HI
	 (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
	 (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
  "TARGET_REALLY_IWMMXT"
  "wpackwus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wpackdus"
  [(set (match_operand:V2SI                0 "register_operand" "=y")
	(vec_concat:V2SI
	 (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
	 (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
  "TARGET_REALLY_IWMMXT"
  "wpackdus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])


(define_insn "iwmmxt_wunpckihb"
  [(set (match_operand:V8QI                   0 "register_operand" "=y")
	(vec_merge:V8QI
	 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
			  (parallel [(const_int 4)
				     (const_int 0)
				     (const_int 5)
				     (const_int 1)
				     (const_int 6)
				     (const_int 2)
				     (const_int 7)
				     (const_int 3)]))
	 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
			  (parallel [(const_int 0)
				     (const_int 4)
				     (const_int 1)
				     (const_int 5)
				     (const_int 2)
				     (const_int 6)
				     (const_int 3)
				     (const_int 7)]))
	 (const_int 85)))]
  "TARGET_REALLY_IWMMXT"
  "wunpckihb%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckihh"
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
	(vec_merge:V4HI
	 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
			  (parallel [(const_int 0)
				     (const_int 2)
				     (const_int 1)
				     (const_int 3)]))
	 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
			  (parallel [(const_int 2)
				     (const_int 0)
				     (const_int 3)
				     (const_int 1)]))
	 (const_int 5)))]
  "TARGET_REALLY_IWMMXT"
  "wunpckihh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckihw"
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
	(vec_merge:V2SI
	 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
			  (parallel [(const_int 0)
				     (const_int 1)]))
	 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
			  (parallel [(const_int 1)
				     (const_int 0)]))
	 (const_int 1)))]
  "TARGET_REALLY_IWMMXT"
  "wunpckihw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckilb"
  [(set (match_operand:V8QI                   0 "register_operand" "=y")
	(vec_merge:V8QI
	 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
			  (parallel [(const_int 0)
				     (const_int 4)
				     (const_int 1)
				     (const_int 5)
				     (const_int 2)
				     (const_int 6)
				     (const_int 3)
				     (const_int 7)]))
	 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
			  (parallel [(const_int 4)
				     (const_int 0)
				     (const_int 5)
				     (const_int 1)
				     (const_int 6)
				     (const_int 2)
				     (const_int 7)
				     (const_int 3)]))
	 (const_int 85)))]
  "TARGET_REALLY_IWMMXT"
  "wunpckilb%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckilh"
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
	(vec_merge:V4HI
	 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
			  (parallel [(const_int 2)
				     (const_int 0)
				     (const_int 3)
				     (const_int 1)]))
	 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
			  (parallel [(const_int 0)
				     (const_int 2)
				     (const_int 1)
				     (const_int 3)]))
	 (const_int 5)))]
  "TARGET_REALLY_IWMMXT"
  "wunpckilh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckilw"
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
	(vec_merge:V2SI
	 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
			   (parallel [(const_int 1)
				      (const_int 0)]))
	 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
			  (parallel [(const_int 0)
				     (const_int 1)]))
	 (const_int 1)))]
  "TARGET_REALLY_IWMMXT"
  "wunpckilw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckehub"
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
	(zero_extend:V4HI
	 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
			  (parallel [(const_int 4) (const_int 5)
				     (const_int 6) (const_int 7)]))))]
  "TARGET_REALLY_IWMMXT"
  "wunpckehub%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckehuh"
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
	(zero_extend:V2SI
	 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
			  (parallel [(const_int 2) (const_int 3)]))))]
  "TARGET_REALLY_IWMMXT"
  "wunpckehuh%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckehuw"
  [(set (match_operand:DI                   0 "register_operand" "=y")
	(zero_extend:DI
	 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
			(parallel [(const_int 1)]))))]
  "TARGET_REALLY_IWMMXT"
  "wunpckehuw%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckehsb"
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
	(sign_extend:V4HI
	 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
			  (parallel [(const_int 4) (const_int 5)
				     (const_int 6) (const_int 7)]))))]
  "TARGET_REALLY_IWMMXT"
  "wunpckehsb%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckehsh"
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
	(sign_extend:V2SI
	 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
			  (parallel [(const_int 2) (const_int 3)]))))]
  "TARGET_REALLY_IWMMXT"
  "wunpckehsh%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckehsw"
  [(set (match_operand:DI                   0 "register_operand" "=y")
	(sign_extend:DI
	 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
			(parallel [(const_int 1)]))))]
  "TARGET_REALLY_IWMMXT"
  "wunpckehsw%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckelub"
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
	(zero_extend:V4HI
	 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
			  (parallel [(const_int 0) (const_int 1)
				     (const_int 2) (const_int 3)]))))]
  "TARGET_REALLY_IWMMXT"
  "wunpckelub%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckeluh"
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
	(zero_extend:V2SI
	 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
			  (parallel [(const_int 0) (const_int 1)]))))]
  "TARGET_REALLY_IWMMXT"
  "wunpckeluh%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckeluw"
  [(set (match_operand:DI                   0 "register_operand" "=y")
	(zero_extend:DI
	 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
			(parallel [(const_int 0)]))))]
  "TARGET_REALLY_IWMMXT"
  "wunpckeluw%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckelsb"
  [(set (match_operand:V4HI                   0 "register_operand" "=y")
	(sign_extend:V4HI
	 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y")
			  (parallel [(const_int 0) (const_int 1)
				     (const_int 2) (const_int 3)]))))]
  "TARGET_REALLY_IWMMXT"
  "wunpckelsb%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckelsh"
  [(set (match_operand:V2SI                   0 "register_operand" "=y")
	(sign_extend:V2SI
	 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y")
			  (parallel [(const_int 0) (const_int 1)]))))]
  "TARGET_REALLY_IWMMXT"
  "wunpckelsh%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wunpckelsw"
  [(set (match_operand:DI                   0 "register_operand" "=y")
	(sign_extend:DI
	 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
			(parallel [(const_int 0)]))))]
  "TARGET_REALLY_IWMMXT"
  "wunpckelsw%?\\t%0, %1"
  [(set_attr "predicable" "yes")])

;; Shifts

(define_insn "rorv4hi3"
  [(set (match_operand:V4HI                0 "register_operand" "=y")
        (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y")
		       (match_operand:SI   2 "register_operand" "z")))]
  "TARGET_REALLY_IWMMXT"
  "wrorhg%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "rorv2si3"
  [(set (match_operand:V2SI                0 "register_operand" "=y")
        (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y")
		       (match_operand:SI   2 "register_operand" "z")))]
  "TARGET_REALLY_IWMMXT"
  "wrorwg%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "rordi3"
  [(set (match_operand:DI              0 "register_operand" "=y")
	(rotatert:DI (match_operand:DI 1 "register_operand" "y")
		   (match_operand:SI   2 "register_operand" "z")))]
  "TARGET_REALLY_IWMMXT"
  "wrordg%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashrv4hi3"
  [(set (match_operand:V4HI                0 "register_operand" "=y")
        (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y")
		       (match_operand:SI   2 "register_operand" "z")))]
  "TARGET_REALLY_IWMMXT"
  "wsrahg%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ashrv2si3"
  [(set (match_operand:V2SI                0 "register_operand" "=y")
        (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y")