iwmmxt.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

  "wmulul%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "smulv4hi3_highpart"
  [(set (match_operand:V4HI                                0 "register_operand" "=y")
	(truncate:V4HI
	 (lshiftrt:V4SI
	  (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
		     (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
	  (const_int 16))))]
  "TARGET_REALLY_IWMMXT"
  "wmulsm%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "umulv4hi3_highpart"
  [(set (match_operand:V4HI                                0 "register_operand" "=y")
	(truncate:V4HI
	 (lshiftrt:V4SI
	  (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
		     (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
	  (const_int 16))))]
  "TARGET_REALLY_IWMMXT"
  "wmulum%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wmacs"
  [(set (match_operand:DI               0 "register_operand" "=y")
	(unspec:DI [(match_operand:DI   1 "register_operand" "0")
		    (match_operand:V4HI 2 "register_operand" "y")
		    (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))]
  "TARGET_REALLY_IWMMXT"
  "wmacs%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wmacsz"
  [(set (match_operand:DI               0 "register_operand" "=y")
	(unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
		    (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))]
  "TARGET_REALLY_IWMMXT"
  "wmacsz%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wmacu"
  [(set (match_operand:DI               0 "register_operand" "=y")
	(unspec:DI [(match_operand:DI   1 "register_operand" "0")
		    (match_operand:V4HI 2 "register_operand" "y")
		    (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))]
  "TARGET_REALLY_IWMMXT"
  "wmacu%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wmacuz"
  [(set (match_operand:DI               0 "register_operand" "=y")
	(unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
		    (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))]
  "TARGET_REALLY_IWMMXT"
  "wmacuz%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

;; Same as xordi3, but don't show input operands so that we don't think
;; they are live.
(define_insn "iwmmxt_clrdi"
  [(set (match_operand:DI 0 "register_operand" "=y")
        (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
  "TARGET_REALLY_IWMMXT"
  "wxor%?\\t%0, %0, %0"
  [(set_attr "predicable" "yes")])

;; Seems like cse likes to generate these, so we have to support them.

(define_insn "*iwmmxt_clrv8qi"
  [(set (match_operand:V8QI 0 "register_operand" "=y")
        (const_vector:V8QI [(const_int 0) (const_int 0)
			    (const_int 0) (const_int 0)
			    (const_int 0) (const_int 0)
			    (const_int 0) (const_int 0)]))]
  "TARGET_REALLY_IWMMXT"
  "wxor%?\\t%0, %0, %0"
  [(set_attr "predicable" "yes")])

(define_insn "*iwmmxt_clrv4hi"
  [(set (match_operand:V4HI 0 "register_operand" "=y")
        (const_vector:V4HI [(const_int 0) (const_int 0)
			    (const_int 0) (const_int 0)]))]
  "TARGET_REALLY_IWMMXT"
  "wxor%?\\t%0, %0, %0"
  [(set_attr "predicable" "yes")])

(define_insn "*iwmmxt_clrv2si"
  [(set (match_operand:V2SI 0 "register_operand" "=y")
        (const_vector:V2SI [(const_int 0) (const_int 0)]))]
  "TARGET_REALLY_IWMMXT"
  "wxor%?\\t%0, %0, %0"
  [(set_attr "predicable" "yes")])

;; Unsigned averages/sum of absolute differences

(define_insn "iwmmxt_uavgrndv8qi3"
  [(set (match_operand:V8QI              0 "register_operand" "=y")
        (ashiftrt:V8QI
	 (plus:V8QI (plus:V8QI
		     (match_operand:V8QI 1 "register_operand" "y")
		     (match_operand:V8QI 2 "register_operand" "y"))
		    (const_vector:V8QI [(const_int 1)
					(const_int 1)
					(const_int 1)
					(const_int 1)
					(const_int 1)
					(const_int 1)
					(const_int 1)
					(const_int 1)]))
	 (const_int 1)))]
  "TARGET_REALLY_IWMMXT"
  "wavg2br%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_uavgrndv4hi3"
  [(set (match_operand:V4HI              0 "register_operand" "=y")
        (ashiftrt:V4HI
	 (plus:V4HI (plus:V4HI
		     (match_operand:V4HI 1 "register_operand" "y")
		     (match_operand:V4HI 2 "register_operand" "y"))
		    (const_vector:V4HI [(const_int 1)
					(const_int 1)
					(const_int 1)
					(const_int 1)]))
	 (const_int 1)))]
  "TARGET_REALLY_IWMMXT"
  "wavg2hr%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])


(define_insn "iwmmxt_uavgv8qi3"
  [(set (match_operand:V8QI                 0 "register_operand" "=y")
        (ashiftrt:V8QI (plus:V8QI
			(match_operand:V8QI 1 "register_operand" "y")
			(match_operand:V8QI 2 "register_operand" "y"))
		       (const_int 1)))]
  "TARGET_REALLY_IWMMXT"
  "wavg2b%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_uavgv4hi3"
  [(set (match_operand:V4HI                 0 "register_operand" "=y")
        (ashiftrt:V4HI (plus:V4HI
			(match_operand:V4HI 1 "register_operand" "y")
			(match_operand:V4HI 2 "register_operand" "y"))
		       (const_int 1)))]
  "TARGET_REALLY_IWMMXT"
  "wavg2h%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_psadbw"
  [(set (match_operand:V8QI                       0 "register_operand" "=y")
        (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
			      (match_operand:V8QI 2 "register_operand" "y"))))]
  "TARGET_REALLY_IWMMXT"
  "psadbw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])


;; Insert/extract/shuffle

(define_insn "iwmmxt_tinsrb"
  [(set (match_operand:V8QI                             0 "register_operand"    "=y")
        (vec_merge:V8QI (match_operand:V8QI             1 "register_operand"     "0")
			(vec_duplicate:V8QI
			 (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
			(match_operand:SI               3 "immediate_operand"    "i")))]
  "TARGET_REALLY_IWMMXT"
  "tinsrb%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tinsrh"
  [(set (match_operand:V4HI                             0 "register_operand"    "=y")
        (vec_merge:V4HI (match_operand:V4HI             1 "register_operand"     "0")
			(vec_duplicate:V4HI
			 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
			(match_operand:SI               3 "immediate_operand"    "i")))]
  "TARGET_REALLY_IWMMXT"
  "tinsrh%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_tinsrw"
  [(set (match_operand:V2SI                 0 "register_operand"    "=y")
        (vec_merge:V2SI (match_operand:V2SI 1 "register_operand"     "0")
			(vec_duplicate:V2SI
			 (match_operand:SI  2 "nonimmediate_operand" "r"))
			(match_operand:SI   3 "immediate_operand"    "i")))]
  "TARGET_REALLY_IWMMXT"
  "tinsrw%?\\t%0, %2, %3"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_textrmub"
  [(set (match_operand:SI                                  0 "register_operand" "=r")
        (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
				       (parallel
					[(match_operand:SI 2 "immediate_operand" "i")]))))]
  "TARGET_REALLY_IWMMXT"
  "textrmub%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_textrmsb"
  [(set (match_operand:SI                                  0 "register_operand" "=r")
        (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
				       (parallel
					[(match_operand:SI 2 "immediate_operand" "i")]))))]
  "TARGET_REALLY_IWMMXT"
  "textrmsb%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_textrmuh"
  [(set (match_operand:SI                                  0 "register_operand" "=r")
        (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
				       (parallel
					[(match_operand:SI 2 "immediate_operand" "i")]))))]
  "TARGET_REALLY_IWMMXT"
  "textrmuh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_textrmsh"
  [(set (match_operand:SI                                  0 "register_operand" "=r")
        (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
				       (parallel
					[(match_operand:SI 2 "immediate_operand" "i")]))))]
  "TARGET_REALLY_IWMMXT"
  "textrmsh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

;; There are signed/unsigned variants of this instruction, but they are
;; pointless.
(define_insn "iwmmxt_textrmw"
  [(set (match_operand:SI                           0 "register_operand" "=r")
        (vec_select:SI (match_operand:V2SI          1 "register_operand" "y")
		       (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
  "TARGET_REALLY_IWMMXT"
  "textrmsw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "iwmmxt_wshufh"
  [(set (match_operand:V4HI               0 "register_operand" "=y")
        (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
		      (match_operand:SI   2 "immediate_operand" "i")] UNSPEC_WSHUFH))]
  "TARGET_REALLY_IWMMXT"
  "wshufh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

;; Mask-generating comparisons
;;
;; Note - you cannot use patterns like these here:
;;
;;   (set:<vector> (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>)))
;;
;; Because GCC will assume that the truth value (1 or 0) is installed
;; into the entire destination vector, (with the '1' going into the least
;; significant element of the vector).  This is not how these instructions
;; behave.
;;
;; Unfortunately the current patterns are illegal.  They are SET insns
;; without a SET in them.  They work in most cases for ordinary code
;; generation, but there are circumstances where they can cause gcc to fail.
;; XXX - FIXME.

(define_insn "eqv8qi3"
  [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
		     (match_operand:V8QI 1 "register_operand"  "y")
		     (match_operand:V8QI 2 "register_operand"  "y")]
		    VUNSPEC_WCMP_EQ)]
  "TARGET_REALLY_IWMMXT"
  "wcmpeqb%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "eqv4hi3"
  [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
		     (match_operand:V4HI 1 "register_operand"  "y")
		     (match_operand:V4HI 2 "register_operand"  "y")]
		    VUNSPEC_WCMP_EQ)]
  "TARGET_REALLY_IWMMXT"
  "wcmpeqh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "eqv2si3"
  [(unspec_volatile:V2SI [(match_operand:V2SI 0 "register_operand" "=y")
			  (match_operand:V2SI 1 "register_operand"  "y")
			  (match_operand:V2SI 2 "register_operand"  "y")]
			 VUNSPEC_WCMP_EQ)]
  "TARGET_REALLY_IWMMXT"
  "wcmpeqw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "gtuv8qi3"
  [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
		     (match_operand:V8QI 1 "register_operand"  "y")
		     (match_operand:V8QI 2 "register_operand"  "y")]
		    VUNSPEC_WCMP_GTU)]
  "TARGET_REALLY_IWMMXT"
  "wcmpgtub%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "gtuv4hi3"
  [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
		     (match_operand:V4HI 1 "register_operand"  "y")
		     (match_operand:V4HI 2 "register_operand"  "y")]
		    VUNSPEC_WCMP_GTU)]
  "TARGET_REALLY_IWMMXT"
  "wcmpgtuh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "gtuv2si3"
  [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
		     (match_operand:V2SI 1 "register_operand"  "y")
		     (match_operand:V2SI 2 "register_operand"  "y")]
		    VUNSPEC_WCMP_GTU)]
  "TARGET_REALLY_IWMMXT"
  "wcmpgtuw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "gtv8qi3"
  [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y")
		     (match_operand:V8QI 1 "register_operand"  "y")
		     (match_operand:V8QI 2 "register_operand"  "y")]
		    VUNSPEC_WCMP_GT)]
  "TARGET_REALLY_IWMMXT"
  "wcmpgtsb%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "gtv4hi3"
  [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y")
		     (match_operand:V4HI 1 "register_operand"  "y")
		     (match_operand:V4HI 2 "register_operand"  "y")]
		    VUNSPEC_WCMP_GT)]
  "TARGET_REALLY_IWMMXT"
  "wcmpgtsh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "gtv2si3"
  [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y")
		     (match_operand:V2SI 1 "register_operand"  "y")
		     (match_operand:V2SI 2 "register_operand"  "y")]
		    VUNSPEC_WCMP_GT)]
  "TARGET_REALLY_IWMMXT"
  "wcmpgtsw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

;; Max/min insns

(define_insn "smaxv8qi3"
  [(set (match_operand:V8QI            0 "register_operand" "=y")
        (smax:V8QI (match_operand:V8QI 1 "register_operand" "y")
		   (match_operand:V8QI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wmaxsb%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "umaxv8qi3"
  [(set (match_operand:V8QI            0 "register_operand" "=y")
        (umax:V8QI (match_operand:V8QI 1 "register_operand" "y")
		   (match_operand:V8QI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wmaxub%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "smaxv4hi3"
  [(set (match_operand:V4HI            0 "register_operand" "=y")
        (smax:V4HI (match_operand:V4HI 1 "register_operand" "y")
		   (match_operand:V4HI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wmaxsh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "umaxv4hi3"
  [(set (match_operand:V4HI            0 "register_operand" "=y")
        (umax:V4HI (match_operand:V4HI 1 "register_operand" "y")
		   (match_operand:V4HI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wmaxuh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "smaxv2si3"
  [(set (match_operand:V2SI            0 "register_operand" "=y")
        (smax:V2SI (match_operand:V2SI 1 "register_operand" "y")
		   (match_operand:V2SI 2 "register_operand" "y")))]