iwmmxt.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

;; Patterns for the Intel Wireless MMX technology architecture.
;; Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc.
;; Contributed by Red Hat.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify it under
;; the terms of the GNU General Public License as published by the Free
;; Software Foundation; either version 2, or (at your option) any later
;; version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.

(define_insn "iwmmxt_iordi3"
  [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
        (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r")
		(match_operand:DI 2 "register_operand"  "y,r,r")))]
  "TARGET_REALLY_IWMMXT"
  "@
   wor%?\\t%0, %1, %2
   #
   #"
  [(set_attr "predicable" "yes")
   (set_attr "length" "4,8,8")])

(define_insn "iwmmxt_xordi3"
  [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
        (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r")
		(match_operand:DI 2 "register_operand"  "y,r,r")))]
  "TARGET_REALLY_IWMMXT"
  "@
   wxor%?\\t%0, %1, %2
   #
   #"
  [(set_attr "predicable" "yes")
   (set_attr "length" "4,8,8")])

(define_insn "iwmmxt_anddi3"
  [(set (match_operand:DI         0 "register_operand" "=y,?&r,?&r")
        (and:DI (match_operand:DI 1 "register_operand" "%y,0,r")
		(match_operand:DI 2 "register_operand"  "y,r,r")))]
  "TARGET_REALLY_IWMMXT"
  "@
   wand%?\\t%0, %1, %2
   #
   #"
  [(set_attr "predicable" "yes")
   (set_attr "length" "4,8,8")])

(define_insn "iwmmxt_nanddi3"
  [(set (match_operand:DI                 0 "register_operand" "=y")
        (and:DI (match_operand:DI         1 "register_operand"  "y")
		(not:DI (match_operand:DI 2 "register_operand"  "y"))))]
  "TARGET_REALLY_IWMMXT"
  "wandn%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "*iwmmxt_arm_movdi"
  [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,y,y,yr,y,yrUy")
	(match_operand:DI 1 "di_operand"              "rIK,mi,r,y,yr,y,yrUy,y"))]
  "TARGET_REALLY_IWMMXT"
  "*
{
  switch (which_alternative)
    {
    default:
      return output_move_double (operands);
    case 3:
      return \"wmov%?\\t%0,%1\";
    case 4:
      return \"tmcrr%?\\t%0,%Q1,%R1\";
    case 5:
      return \"tmrrc%?\\t%Q0,%R0,%1\";
    case 6:
      return \"wldrd%?\\t%0,%1\";
    case 7:
      return \"wstrd%?\\t%1,%0\";
    }
}"
  [(set_attr "length"         "8,8,8,4,4,4,4,4")
   (set_attr "type"           "*,load1,store2,*,*,*,*,*")
   (set_attr "pool_range"     "*,1020,*,*,*,*,*,*")
   (set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")]
)

(define_insn "*iwmmxt_movsi_insn"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r,?z,Uy,z")
	(match_operand:SI 1 "general_operand"      "rI,K,mi,r,r,z,Uy,z,z"))]
  "TARGET_REALLY_IWMMXT
   && (   register_operand (operands[0], SImode)
       || register_operand (operands[1], SImode))"
  "*
   switch (which_alternative)
   {
   case 0: return \"mov\\t%0, %1\";
   case 1: return \"mvn\\t%0, #%B1\";
   case 2: return \"ldr\\t%0, %1\";
   case 3: return \"str\\t%1, %0\";
   case 4: return \"tmcr\\t%0, %1\";
   case 5: return \"tmrc\\t%0, %1\";
   case 6: return arm_output_load_gr (operands);
   case 7: return \"wstrw\\t%1, %0\";
   default:return \"wstrw\\t%1, [sp, #-4]!\;wldrw\\t%0, [sp], #4\\t@move CG reg\";
  }"
  [(set_attr "type"           "*,*,load1,store1,*,*,load1,store1,*")
   (set_attr "length"         "*,*,*,        *,*,*,  16,     *,8")
   (set_attr "pool_range"     "*,*,4096,     *,*,*,1024,     *,*")
   (set_attr "neg_pool_range" "*,*,4084,     *,*,*,   *,  1012,*")
   ;; Note - the "predicable" attribute is not allowed to have alternatives.
   ;; Since the wSTRw wCx instruction is not predicable, we cannot support
   ;; predicating any of the alternatives in this template.  Instead,
   ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn.
   (set_attr "predicable"     "no")
   ;; Also - we have to pretend that these insns clobber the condition code
   ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize
   ;; them.
   (set_attr "conds" "clob")]
)

;; Because iwmmxt_movsi_insn is not predicable, we provide the
;; cond_exec version explicitly, with appropriate constraints.

(define_insn "*cond_iwmmxt_movsi_insn"
  [(cond_exec
     (match_operator 2 "arm_comparison_operator"
      [(match_operand 3 "cc_register" "")
      (const_int 0)])
     (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r")
	  (match_operand:SI 1 "general_operand"      "rI,K,mi,r,r,z")))]
  "TARGET_REALLY_IWMMXT
   && (   register_operand (operands[0], SImode)
       || register_operand (operands[1], SImode))"
  "*
   switch (which_alternative)
   {
   case 0: return \"mov%?\\t%0, %1\";
   case 1: return \"mvn%?\\t%0, #%B1\";
   case 2: return \"ldr%?\\t%0, %1\";
   case 3: return \"str%?\\t%1, %0\";
   case 4: return \"tmcr%?\\t%0, %1\";
   default: return \"tmrc%?\\t%0, %1\";
  }"
  [(set_attr "type"           "*,*,load1,store1,*,*")
   (set_attr "pool_range"     "*,*,4096,     *,*,*")
   (set_attr "neg_pool_range" "*,*,4084,     *,*,*")]
)

(define_insn "movv8qi_internal"
  [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r")
	(match_operand:V8QI 1 "general_operand"       "y,y,m,y,r,i"))]
  "TARGET_REALLY_IWMMXT"
  "*
   switch (which_alternative)
   {
   case 0: return \"wmov%?\\t%0, %1\";
   case 1: return \"wstrd%?\\t%1, %0\";
   case 2: return \"wldrd%?\\t%0, %1\";
   case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
   case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
   default: return output_move_double (operands);
   }"
  [(set_attr "predicable" "yes")
   (set_attr "length"         "4,     4,   4,4,4,   8")
   (set_attr "type"           "*,store1,load1,*,*,load1")
   (set_attr "pool_range"     "*,     *, 256,*,*, 256")
   (set_attr "neg_pool_range" "*,     *, 244,*,*, 244")])

(define_insn "movv4hi_internal"
  [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r")
	(match_operand:V4HI 1 "general_operand"       "y,y,m,y,r,i"))]
  "TARGET_REALLY_IWMMXT"
  "*
   switch (which_alternative)
   {
   case 0: return \"wmov%?\\t%0, %1\";
   case 1: return \"wstrd%?\\t%1, %0\";
   case 2: return \"wldrd%?\\t%0, %1\";
   case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
   case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
   default: return output_move_double (operands);
   }"
  [(set_attr "predicable" "yes")
   (set_attr "length"         "4,     4,   4,4,4,   8")
   (set_attr "type"           "*,store1,load1,*,*,load1")
   (set_attr "pool_range"     "*,     *, 256,*,*, 256")
   (set_attr "neg_pool_range" "*,     *, 244,*,*, 244")])

(define_insn "movv2si_internal"
  [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r")
	(match_operand:V2SI 1 "general_operand"       "y,y,m,y,r,i"))]
  "TARGET_REALLY_IWMMXT"
  "*
   switch (which_alternative)
   {
   case 0: return \"wmov%?\\t%0, %1\";
   case 1: return \"wstrd%?\\t%1, %0\";
   case 2: return \"wldrd%?\\t%0, %1\";
   case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
   case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
   default: return output_move_double (operands);
   }"
  [(set_attr "predicable" "yes")
   (set_attr "length"         "4,     4,   4,4,4,  24")
   (set_attr "type"           "*,store1,load1,*,*,load1")
   (set_attr "pool_range"     "*,     *, 256,*,*, 256")
   (set_attr "neg_pool_range" "*,     *, 244,*,*, 244")])

;; This pattern should not be needed.  It is to match a
;; wierd case generated by GCC when no optimizations are
;; enabled.  (Try compiling gcc/testsuite/gcc.c-torture/
;; compile/simd-5.c at -O0).  The mode for operands[1] is
;; deliberately omitted.
(define_insn "movv2si_internal_2"
  [(set (match_operand:V2SI 0 "nonimmediate_operand" "=?r")
	(match_operand      1 "immediate_operand"      "i"))]
  "TARGET_REALLY_IWMMXT"
  "* return output_move_double (operands);"
  [(set_attr "predicable"     "yes")
   (set_attr "length"         "8")
   (set_attr "type"           "load1")
   (set_attr "pool_range"     "256")
   (set_attr "neg_pool_range" "244")])

;; Vector add/subtract

(define_insn "addv8qi3"
  [(set (match_operand:V8QI            0 "register_operand" "=y")
        (plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
	           (match_operand:V8QI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "waddb%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "addv4hi3"
  [(set (match_operand:V4HI            0 "register_operand" "=y")
        (plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
	           (match_operand:V4HI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "waddh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "addv2si3"
  [(set (match_operand:V2SI            0 "register_operand" "=y")
        (plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
	           (match_operand:V2SI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "waddw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ssaddv8qi3"
  [(set (match_operand:V8QI               0 "register_operand" "=y")
        (ss_plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
		      (match_operand:V8QI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "waddbss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ssaddv4hi3"
  [(set (match_operand:V4HI               0 "register_operand" "=y")
        (ss_plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
		      (match_operand:V4HI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "waddhss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ssaddv2si3"
  [(set (match_operand:V2SI               0 "register_operand" "=y")
        (ss_plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
		      (match_operand:V2SI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "waddwss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "usaddv8qi3"
  [(set (match_operand:V8QI               0 "register_operand" "=y")
        (us_plus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
		      (match_operand:V8QI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "waddbus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "usaddv4hi3"
  [(set (match_operand:V4HI               0 "register_operand" "=y")
        (us_plus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
		      (match_operand:V4HI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "waddhus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "usaddv2si3"
  [(set (match_operand:V2SI               0 "register_operand" "=y")
        (us_plus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
		      (match_operand:V2SI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "waddwus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "subv8qi3"
  [(set (match_operand:V8QI             0 "register_operand" "=y")
        (minus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
		    (match_operand:V8QI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsubb%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "subv4hi3"
  [(set (match_operand:V4HI             0 "register_operand" "=y")
        (minus:V4HI (match_operand:V4HI 1 "register_operand"  "y")
		    (match_operand:V4HI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsubh%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "subv2si3"
  [(set (match_operand:V2SI             0 "register_operand" "=y")
        (minus:V2SI (match_operand:V2SI 1 "register_operand"  "y")
		    (match_operand:V2SI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsubw%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "sssubv8qi3"
  [(set (match_operand:V8QI                0 "register_operand" "=y")
        (ss_minus:V8QI (match_operand:V8QI 1 "register_operand"  "y")
		       (match_operand:V8QI 2 "register_operand"  "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsubbss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "sssubv4hi3"
  [(set (match_operand:V4HI                0 "register_operand" "=y")
        (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
		       (match_operand:V4HI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsubhss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "sssubv2si3"
  [(set (match_operand:V2SI                0 "register_operand" "=y")
        (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
		       (match_operand:V2SI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsubwss%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ussubv8qi3"
  [(set (match_operand:V8QI                0 "register_operand" "=y")
        (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
		       (match_operand:V8QI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsubbus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ussubv4hi3"
  [(set (match_operand:V4HI                0 "register_operand" "=y")
        (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
		       (match_operand:V4HI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsubhus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "ussubv2si3"
  [(set (match_operand:V2SI                0 "register_operand" "=y")
        (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
		       (match_operand:V2SI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"
  "wsubwus%?\\t%0, %1, %2"
  [(set_attr "predicable" "yes")])

(define_insn "mulv4hi3"
  [(set (match_operand:V4HI            0 "register_operand" "=y")
        (mult:V4HI (match_operand:V4HI 1 "register_operand" "y")
		   (match_operand:V4HI 2 "register_operand" "y")))]
  "TARGET_REALLY_IWMMXT"