fpa.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

;;- Machine description for FPA co-processor for ARM cpus.
;;  Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000,
;;  2001, 2002, 2003, 2004, 2005  Free Software Foundation, Inc.
;;  Contributed by Pieter `Tiggr' Schoenmakers ([e-mail])
;;  and Martin Simmons (@harleqn.co.uk).
;;  More major hacks by Richard Earnshaw ([e-mail]).

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 2, or (at your
;; option) any later version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.

;; FPA automaton.
(define_automaton "armfp")

;; Floating point unit (FPA)
(define_cpu_unit "fpa" "armfp")

; The fpa10 doesn't really have a memory read unit, but it can start
; to speculatively execute the instruction in the pipeline, provided
; the data is already loaded, so pretend reads have a delay of 2 (and
; that the pipeline is infinite).
(define_cpu_unit "fpa_mem" "arm")

(define_insn_reservation "fdivx" 71
  (and (eq_attr "fpu" "fpa")
       (eq_attr "type" "fdivx"))
  "core+fpa*69")

(define_insn_reservation "fdivd" 59
  (and (eq_attr "fpu" "fpa")
       (eq_attr "type" "fdivd"))
  "core+fpa*57")

(define_insn_reservation "fdivs" 31
  (and (eq_attr "fpu" "fpa")
       (eq_attr "type" "fdivs"))
  "core+fpa*29")

(define_insn_reservation "fmul" 9
  (and (eq_attr "fpu" "fpa")
       (eq_attr "type" "fmul"))
  "core+fpa*7")

(define_insn_reservation "ffmul" 6
  (and (eq_attr "fpu" "fpa")
       (eq_attr "type" "ffmul"))
  "core+fpa*4")

(define_insn_reservation "farith" 4
  (and (eq_attr "fpu" "fpa")
       (eq_attr "type" "farith"))
  "core+fpa*2")

(define_insn_reservation "ffarith" 2
  (and (eq_attr "fpu" "fpa")
       (eq_attr "type" "ffarith"))
  "core+fpa*2")

(define_insn_reservation "r_2_f" 5
  (and (eq_attr "fpu" "fpa")
       (eq_attr "type" "r_2_f"))
  "core+fpa*3")

(define_insn_reservation "f_2_r" 1
  (and (eq_attr "fpu" "fpa")
       (eq_attr "type" "f_2_r"))
  "core+fpa*2")

(define_insn_reservation "f_load" 3
  (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_load"))
  "fpa_mem+core*3")

(define_insn_reservation "f_store" 4
  (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_store"))
  "core*4")

(define_insn_reservation "r_mem_f" 6
  (and (eq_attr "model_wbuf" "no")
    (and (eq_attr "fpu" "fpa") (eq_attr "type" "r_mem_f")))
  "core*6")

(define_insn_reservation "f_mem_r" 7
  (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_mem_r"))
  "core*7")


(define_insn "*addsf3_fpa"
  [(set (match_operand:SF          0 "s_register_operand" "=f,f")
	(plus:SF (match_operand:SF 1 "s_register_operand" "%f,f")
		 (match_operand:SF 2 "arm_float_add_operand"    "fG,H")))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "@
   adf%?s\\t%0, %1, %2
   suf%?s\\t%0, %1, #%N2"
  [(set_attr "type" "farith")
   (set_attr "predicable" "yes")]
)

(define_insn "*adddf3_fpa"
  [(set (match_operand:DF          0 "s_register_operand" "=f,f")
	(plus:DF (match_operand:DF 1 "s_register_operand" "%f,f")
		 (match_operand:DF 2 "arm_float_add_operand"    "fG,H")))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "@
   adf%?d\\t%0, %1, %2
   suf%?d\\t%0, %1, #%N2"
  [(set_attr "type" "farith")
   (set_attr "predicable" "yes")]
)

(define_insn "*adddf_esfdf_df_fpa"
  [(set (match_operand:DF           0 "s_register_operand" "=f,f")
	(plus:DF (float_extend:DF
		  (match_operand:SF 1 "s_register_operand"  "f,f"))
		 (match_operand:DF  2 "arm_float_add_operand"    "fG,H")))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "@
   adf%?d\\t%0, %1, %2
   suf%?d\\t%0, %1, #%N2"
  [(set_attr "type" "farith")
   (set_attr "predicable" "yes")]
)

(define_insn "*adddf_df_esfdf_fpa"
  [(set (match_operand:DF           0 "s_register_operand" "=f")
	(plus:DF (match_operand:DF  1 "s_register_operand"  "f")
		 (float_extend:DF
		  (match_operand:SF 2 "s_register_operand"  "f"))))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "adf%?d\\t%0, %1, %2"
  [(set_attr "type" "farith")
   (set_attr "predicable" "yes")]
)

(define_insn "*adddf_esfdf_esfdf_fpa"
  [(set (match_operand:DF           0 "s_register_operand" "=f")
	(plus:DF (float_extend:DF 
		  (match_operand:SF 1 "s_register_operand" "f"))
		 (float_extend:DF
		  (match_operand:SF 2 "s_register_operand" "f"))))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "adf%?d\\t%0, %1, %2"
  [(set_attr "type" "farith")
   (set_attr "predicable" "yes")]
)

(define_insn "*subsf3_fpa"
  [(set (match_operand:SF 0 "s_register_operand" "=f,f")
	(minus:SF (match_operand:SF 1 "arm_float_rhs_operand" "f,G")
		  (match_operand:SF 2 "arm_float_rhs_operand" "fG,f")))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "@
   suf%?s\\t%0, %1, %2
   rsf%?s\\t%0, %2, %1"
  [(set_attr "type" "farith")]
)

(define_insn "*subdf3_fpa"
  [(set (match_operand:DF           0 "s_register_operand" "=f,f")
	(minus:DF (match_operand:DF 1 "arm_float_rhs_operand"     "f,G")
		  (match_operand:DF 2 "arm_float_rhs_operand"    "fG,f")))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "@
   suf%?d\\t%0, %1, %2
   rsf%?d\\t%0, %2, %1"
  [(set_attr "type" "farith")
   (set_attr "predicable" "yes")]
)

(define_insn "*subdf_esfdf_df_fpa"
  [(set (match_operand:DF            0 "s_register_operand" "=f")
	(minus:DF (float_extend:DF
		   (match_operand:SF 1 "s_register_operand"  "f"))
		  (match_operand:DF  2 "arm_float_rhs_operand"    "fG")))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "suf%?d\\t%0, %1, %2"
  [(set_attr "type" "farith")
   (set_attr "predicable" "yes")]
)

(define_insn "*subdf_df_esfdf_fpa"
  [(set (match_operand:DF 0 "s_register_operand" "=f,f")
	(minus:DF (match_operand:DF 1 "arm_float_rhs_operand" "f,G")
		  (float_extend:DF
		   (match_operand:SF 2 "s_register_operand" "f,f"))))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "@
   suf%?d\\t%0, %1, %2
   rsf%?d\\t%0, %2, %1"
  [(set_attr "type" "farith")
   (set_attr "predicable" "yes")]
)

(define_insn "*subdf_esfdf_esfdf_fpa"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(minus:DF (float_extend:DF
		   (match_operand:SF 1 "s_register_operand" "f"))
		  (float_extend:DF
		   (match_operand:SF 2 "s_register_operand" "f"))))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "suf%?d\\t%0, %1, %2"
  [(set_attr "type" "farith")
   (set_attr "predicable" "yes")]
)

(define_insn "*mulsf3_fpa"
  [(set (match_operand:SF 0 "s_register_operand" "=f")
	(mult:SF (match_operand:SF 1 "s_register_operand" "f")
		 (match_operand:SF 2 "arm_float_rhs_operand" "fG")))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "fml%?s\\t%0, %1, %2"
  [(set_attr "type" "ffmul")
   (set_attr "predicable" "yes")]
)

(define_insn "*muldf3_fpa"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(mult:DF (match_operand:DF 1 "s_register_operand" "f")
		 (match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "muf%?d\\t%0, %1, %2"
  [(set_attr "type" "fmul")
   (set_attr "predicable" "yes")]
)

(define_insn "*muldf_esfdf_df_fpa"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(mult:DF (float_extend:DF
		  (match_operand:SF 1 "s_register_operand" "f"))
		 (match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "muf%?d\\t%0, %1, %2"
  [(set_attr "type" "fmul")
   (set_attr "predicable" "yes")]
)

(define_insn "*muldf_df_esfdf_fpa"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(mult:DF (match_operand:DF 1 "s_register_operand" "f")
		 (float_extend:DF
		  (match_operand:SF 2 "s_register_operand" "f"))))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "muf%?d\\t%0, %1, %2"
  [(set_attr "type" "fmul")
   (set_attr "predicable" "yes")]
)

(define_insn "*muldf_esfdf_esfdf_fpa"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(mult:DF
	 (float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))
	 (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "muf%?d\\t%0, %1, %2"
  [(set_attr "type" "fmul")
   (set_attr "predicable" "yes")]
)

;; Division insns

(define_insn "*divsf3_fpa"
  [(set (match_operand:SF 0 "s_register_operand" "=f,f")
	(div:SF (match_operand:SF 1 "arm_float_rhs_operand" "f,G")
		(match_operand:SF 2 "arm_float_rhs_operand" "fG,f")))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "@
   fdv%?s\\t%0, %1, %2
   frd%?s\\t%0, %2, %1"
  [(set_attr "type" "fdivs")
   (set_attr "predicable" "yes")]
)

(define_insn "*divdf3_fpa"
  [(set (match_operand:DF 0 "s_register_operand" "=f,f")
	(div:DF (match_operand:DF 1 "arm_float_rhs_operand" "f,G")
		(match_operand:DF 2 "arm_float_rhs_operand" "fG,f")))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "@
   dvf%?d\\t%0, %1, %2
   rdf%?d\\t%0, %2, %1"
  [(set_attr "type" "fdivd")
   (set_attr "predicable" "yes")]
)

(define_insn "*divdf_esfdf_df_fpa"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(div:DF (float_extend:DF
		 (match_operand:SF 1 "s_register_operand" "f"))
		(match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "dvf%?d\\t%0, %1, %2"
  [(set_attr "type" "fdivd")
   (set_attr "predicable" "yes")]
)

(define_insn "*divdf_df_esfdf_fpa"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(div:DF (match_operand:DF 1 "arm_float_rhs_operand" "fG")
		(float_extend:DF
		 (match_operand:SF 2 "s_register_operand" "f"))))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "rdf%?d\\t%0, %2, %1"
  [(set_attr "type" "fdivd")
   (set_attr "predicable" "yes")]
)

(define_insn "*divdf_esfdf_esfdf_fpa"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(div:DF (float_extend:DF
		 (match_operand:SF 1 "s_register_operand" "f"))
		(float_extend:DF
		 (match_operand:SF 2 "s_register_operand" "f"))))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "dvf%?d\\t%0, %1, %2"
  [(set_attr "type" "fdivd")
   (set_attr "predicable" "yes")]
)

(define_insn "*modsf3_fpa"
  [(set (match_operand:SF 0 "s_register_operand" "=f")
	(mod:SF (match_operand:SF 1 "s_register_operand" "f")
		(match_operand:SF 2 "arm_float_rhs_operand" "fG")))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "rmf%?s\\t%0, %1, %2"
  [(set_attr "type" "fdivs")
   (set_attr "predicable" "yes")]
)

(define_insn "*moddf3_fpa"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(mod:DF (match_operand:DF 1 "s_register_operand" "f")
		(match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "rmf%?d\\t%0, %1, %2"
  [(set_attr "type" "fdivd")
   (set_attr "predicable" "yes")]
)

(define_insn "*moddf_esfdf_df_fpa"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(mod:DF (float_extend:DF
		 (match_operand:SF 1 "s_register_operand" "f"))
		(match_operand:DF 2 "arm_float_rhs_operand" "fG")))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "rmf%?d\\t%0, %1, %2"
  [(set_attr "type" "fdivd")
   (set_attr "predicable" "yes")]
)

(define_insn "*moddf_df_esfdf_fpa"
  [(set (match_operand:DF 0 "s_register_operand" "=f")
	(mod:DF (match_operand:DF 1 "s_register_operand" "f")
		(float_extend:DF
		 (match_operand:SF 2 "s_register_operand" "f"))))]
  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
  "rmf%?d\\t%0, %1, %2"
  [(set_attr "type" "fdivd")
   (set_attr "predicable" "yes")]
)

(define_insn "*moddf_esfdf_esfdf_fpa"
  [(set (match_operand:DF 0 "s_register_operand" "=f")