avr.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

   (clobber (reg:HI 30))]
  "AVR_ENHANCED"
  "%~call __mulsi3"
  [(set_attr "type" "xcall")
   (set_attr "cc" "clobber")])

; / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / %
; divmod

;; Generate libgcc.S calls ourselves, because:
;;  - we know exactly which registers are clobbered (for QI and HI
;;    modes, some of the call-used registers are preserved)
;;  - we get both the quotient and the remainder at no extra cost

(define_expand "divmodqi4"
  [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
   (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
   (parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
	      (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
	      (clobber (reg:QI 22))
	      (clobber (reg:QI 23))])
   (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))
   (set (match_operand:QI 3 "register_operand" "") (reg:QI 25))]
  ""
  "")

(define_insn "*divmodqi4_call"
  [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
   (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
   (clobber (reg:QI 22))
   (clobber (reg:QI 23))]
  ""
  "%~call __divmodqi4"
  [(set_attr "type" "xcall")
   (set_attr "cc" "clobber")])

(define_expand "udivmodqi4"
  [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
   (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
   (parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
	      (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
	      (clobber (reg:QI 23))])
   (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))
   (set (match_operand:QI 3 "register_operand" "") (reg:QI 25))]
  ""
  "")

(define_insn "*udivmodqi4_call"
  [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
   (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
   (clobber (reg:QI 23))]
  ""
  "%~call __udivmodqi4"
  [(set_attr "type" "xcall")
   (set_attr "cc" "clobber")])

(define_expand "divmodhi4"
  [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
   (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
   (parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
	      (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
	      (clobber (reg:HI 26))
	      (clobber (reg:QI 21))])
   (set (match_operand:HI 0 "register_operand" "") (reg:HI 22))
   (set (match_operand:HI 3 "register_operand" "") (reg:HI 24))]
  ""
  "")

(define_insn "*divmodhi4_call"
  [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
   (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
   (clobber (reg:HI 26))
   (clobber (reg:QI 21))]
  ""
  "%~call __divmodhi4"
  [(set_attr "type" "xcall")
   (set_attr "cc" "clobber")])

(define_expand "udivmodhi4"
  [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
   (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
   (parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
	      (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
	      (clobber (reg:HI 26))
	      (clobber (reg:QI 21))])
   (set (match_operand:HI 0 "register_operand" "") (reg:HI 22))
   (set (match_operand:HI 3 "register_operand" "") (reg:HI 24))]
  ""
  "")

(define_insn "*udivmodhi4_call"
  [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
   (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
   (clobber (reg:HI 26))
   (clobber (reg:QI 21))]
  ""
  "%~call __udivmodhi4"
  [(set_attr "type" "xcall")
   (set_attr "cc" "clobber")])

(define_expand "divmodsi4"
  [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
   (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
   (parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
	      (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
	      (clobber (reg:HI 26))
	      (clobber (reg:HI 30))])
   (set (match_operand:SI 0 "register_operand" "") (reg:SI 18))
   (set (match_operand:SI 3 "register_operand" "") (reg:SI 22))]
  ""
  "")

(define_insn "*divmodsi4_call"
  [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
   (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
   (clobber (reg:HI 26))
   (clobber (reg:HI 30))]
  ""
  "%~call __divmodsi4"
  [(set_attr "type" "xcall")
   (set_attr "cc" "clobber")])

(define_expand "udivmodsi4"
  [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
   (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
   (parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
	      (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
	      (clobber (reg:HI 26))
	      (clobber (reg:HI 30))])
   (set (match_operand:SI 0 "register_operand" "") (reg:SI 18))
   (set (match_operand:SI 3 "register_operand" "") (reg:SI 22))]
  ""
  "")

(define_insn "*udivmodsi4_call"
  [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
   (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
   (clobber (reg:HI 26))
   (clobber (reg:HI 30))]
  ""
  "%~call __udivmodsi4"
  [(set_attr "type" "xcall")
   (set_attr "cc" "clobber")])

;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
; and

(define_insn "andqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,d")
        (and:QI (match_operand:QI 1 "register_operand" "%0,0")
                (match_operand:QI 2 "nonmemory_operand" "r,i")))]
  ""
  "@
	and %0,%2
	andi %0,lo8(%2)"
  [(set_attr "length" "1,1")
   (set_attr "cc" "set_zn,set_zn")])

(define_insn "andhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,d,r")
	  (and:HI (match_operand:HI 1 "register_operand" "%0,0,0")
		  (match_operand:HI 2 "nonmemory_operand" "r,i,M")))
   (clobber (match_scratch:QI 3 "=X,X,&d"))]
  ""
  "*{
  if (which_alternative==0)
    return (AS2 (and,%A0,%A2) CR_TAB
	    AS2 (and,%B0,%B2));
  else if (which_alternative==1)
    {
      if (GET_CODE (operands[2]) == CONST_INT)
        {
	  int mask = INTVAL (operands[2]);
	  if ((mask & 0xff) != 0xff)
	    output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
	  if ((mask & 0xff00) != 0xff00)
	    output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
	  return \"\";
        }
        return (AS2 (andi,%A0,lo8(%2)) CR_TAB
	        AS2 (andi,%B0,hi8(%2)));
     }
  return (AS2 (ldi,%3,lo8(%2)) CR_TAB
          AS2 (and,%A0,%3)     CR_TAB
          AS1 (clr,%B0));
}"
  [(set_attr "length" "2,2,3")
   (set_attr "cc" "set_n,clobber,set_n")])

(define_insn "andsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,d")
	(and:SI (match_operand:SI 1 "register_operand" "%0,0")
		(match_operand:SI 2 "nonmemory_operand" "r,i")))]
  ""
  "*{
  if (which_alternative==0)
    return (AS2 (and, %0,%2)   CR_TAB
	    AS2 (and, %B0,%B2) CR_TAB
	    AS2 (and, %C0,%C2) CR_TAB
	    AS2 (and, %D0,%D2));
  else if (which_alternative==1)
    {
      if (GET_CODE (operands[2]) == CONST_INT)
        {
	  HOST_WIDE_INT mask = INTVAL (operands[2]);
	  if ((mask & 0xff) != 0xff)
	    output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
	  if ((mask & 0xff00) != 0xff00)
	    output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
	  if ((mask & 0xff0000L) != 0xff0000L)
	    output_asm_insn (AS2 (andi,%C0,hlo8(%2)), operands);
	  if ((mask & 0xff000000L) != 0xff000000L)
	    output_asm_insn (AS2 (andi,%D0,hhi8(%2)), operands);
	  return \"\";
        }
      return (AS2 (andi, %A0,lo8(%2))  CR_TAB
              AS2 (andi, %B0,hi8(%2)) CR_TAB
	      AS2 (andi, %C0,hlo8(%2)) CR_TAB
	      AS2 (andi, %D0,hhi8(%2)));
    }
  return \"bug\";
}"
  [(set_attr "length" "4,4")
   (set_attr "cc" "set_n,set_n")])

;;|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
;; ior

(define_insn "iorqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,d")
        (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
                (match_operand:QI 2 "nonmemory_operand" "r,i")))]
  ""
  "@
	or %0,%2
	ori %0,lo8(%2)"
  [(set_attr "length" "1,1")
   (set_attr "cc" "set_zn,set_zn")])

(define_insn "iorhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,d")
	(ior:HI (match_operand:HI 1 "register_operand" "%0,0")
		(match_operand:HI 2 "nonmemory_operand" "r,i")))]
  ""
  "*{
  if (which_alternative==0)
    return (AS2 (or,%A0,%A2) CR_TAB
	    AS2 (or,%B0,%B2));
  if (GET_CODE (operands[2]) == CONST_INT)
     {
	int mask = INTVAL (operands[2]);
	if (mask & 0xff)
	  output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
	if (mask & 0xff00)
	  output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
	return \"\";
      }
   return (AS2 (ori,%0,lo8(%2)) CR_TAB
	   AS2 (ori,%B0,hi8(%2)));
}"  
  [(set_attr "length" "2,2")
   (set_attr "cc" "set_n,clobber")])

(define_insn "*iorhi3_clobber"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
	(ior:HI (match_operand:HI 1 "register_operand" "%0,0")
		(match_operand:HI 2 "immediate_operand" "M,i")))
   (clobber (match_scratch:QI 3 "=&d,&d"))]
  ""
  "@
	ldi %3,lo8(%2)\;or %A0,%3
	ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3"
  [(set_attr "length" "2,4")
   (set_attr "cc" "clobber,set_n")])

(define_insn "iorsi3"
  [(set (match_operand:SI 0 "register_operand"        "=r,d")
	(ior:SI (match_operand:SI 1 "register_operand" "%0,0")
		(match_operand:SI 2 "nonmemory_operand" "r,i")))]
  ""
  "*{
  if (which_alternative==0)
    return (AS2 (or, %0,%2)   CR_TAB
	    AS2 (or, %B0,%B2) CR_TAB
	    AS2 (or, %C0,%C2) CR_TAB
	    AS2 (or, %D0,%D2));
  if (GET_CODE (operands[2]) == CONST_INT)
     {
	HOST_WIDE_INT mask = INTVAL (operands[2]);
	if (mask & 0xff)
	  output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
	if (mask & 0xff00)
	  output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
	if (mask & 0xff0000L)
	  output_asm_insn (AS2 (ori,%C0,hlo8(%2)), operands);
	if (mask & 0xff000000L)
	  output_asm_insn (AS2 (ori,%D0,hhi8(%2)), operands);
	return \"\";
      }
  return (AS2 (ori, %A0,lo8(%2))  CR_TAB
	  AS2 (ori, %B0,hi8(%2)) CR_TAB
	  AS2 (ori, %C0,hlo8(%2)) CR_TAB
	  AS2 (ori, %D0,hhi8(%2)));
}"
  [(set_attr "length" "4,4")
   (set_attr "cc" "set_n,clobber")])

(define_insn "*iorsi3_clobber"
  [(set (match_operand:SI 0 "register_operand"        "=r,r")
	(ior:SI (match_operand:SI 1 "register_operand" "%0,0")
		(match_operand:SI 2 "immediate_operand" "M,i")))
   (clobber (match_scratch:QI 3 "=&d,&d"))]
  ""
  "@
	ldi %3,lo8(%2)\;or %A0,%3
	ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3\;ldi %3,hlo8(%2)\;or %C0,%3\;ldi %3,hhi8(%2)\;or %D0,%3"
  [(set_attr "length" "2,8")
   (set_attr "cc" "clobber,set_n")])

;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
;; xor

(define_insn "xorqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
        (xor:QI (match_operand:QI 1 "register_operand" "%0")
                (match_operand:QI 2 "register_operand" "r")))]
  ""
  "eor %0,%2"
  [(set_attr "length" "1")
   (set_attr "cc" "set_zn")])

(define_insn "xorhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (xor:HI (match_operand:HI 1 "register_operand" "%0")
                (match_operand:HI 2 "register_operand" "r")))]
  ""
  "eor %0,%2
	eor %B0,%B2"
  [(set_attr "length" "2")
   (set_attr "cc" "set_n")])

(define_insn "xorsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (xor:SI (match_operand:SI 1 "register_operand" "%0")
                (match_operand:SI 2 "register_operand" "r")))]
  ""
  "eor %0,%2
	eor %B0,%B2
	eor %C0,%C2
	eor %D0,%D2"
  [(set_attr "length" "4")
   (set_attr "cc" "set_n")])

;;<< << << << << << << << << << << << << << << << << << << << << << << << << <<
;; arithmetic shift left

(define_insn "ashlqi3"
  [(set (match_operand:QI 0 "register_operand"           "=r,r,r,r,!d,r,r")
	(ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
		   (match_operand:QI 2 "general_operand"  "r,L,P,K,n,n,Qm")))]
  ""
  "* return ashlqi3_out (insn, operands, NULL);"
  [(set_attr "length" "5,0,1,2,4,6,9")
   (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])

(define_insn "ashlhi3"
  [(set (match_operand:HI 0 "register_operand"           "=r,r,r,r,r,r,r")
	(ashift:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
		   (match_operand:QI 2 "general_operand"  "r,L,P,O,K,n,Qm")))]
  ""
  "* return ashlhi3_out (insn, operands, NULL);"
  [(set_attr "length" "6,0,2,2,4,10,10")
   (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])

(define_insn "ashlsi3"
  [(set (match_operand:SI 0 "register_operand"           "=r,r,r,r,r,r,r")
	(ashift:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
		   (match_operand:QI 2 "general_operand"  "r,L,P,O,K,n,Qm")))]
  ""
  "* return ashlsi3_out (insn, operands, NULL);"
  [(set_attr "length" "8,0,4,4,8,10,12")
   (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])

;; Optimize if a scratch register from LD_REGS happens to be available.

(define_peephole2
  [(match_scratch:QI 3 "d")
   (set (match_operand:HI 0 "register_operand" "")
	(ashift:HI (match_operand:HI 1 "register_operand" "")
		   (match_operand:QI 2 "const_int_operand" "")))]
  ""
  [(parallel [(set (match_dup 0) (ashift:HI (match_dup 1) (match_dup 2)))
	      (clobber (match_dup 3))])]
  "if (!avr_peep2_scratch_safe (operands[3]))
     FAIL;")

(define_insn "*ashlhi3_const"
  [(set (match_operand:HI 0 "register_operand"            "=r,r,r,r,r")
	(ashift:HI (match_operand:HI 1 "register_operand"  "0,0,r,0,0")
		   (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
   (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
  "reload_completed"
  "* return ashlhi3_out (insn, operands, NULL);"
  [(set_attr "length" "0,2,2,4,10")