mcore.h

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

/* Definitions of target machine for GNU compiler,
   for Motorola M*CORE Processor.
   Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004
   Free Software Foundation, Inc.

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published
   by the Free Software Foundation; either version 2, or (at your
   option) any later version.

   GCC is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with GCC; see the file COPYING.  If not, write to the
   Free Software Foundation, 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */

#ifndef GCC_MCORE_H
#define GCC_MCORE_H

/* RBE: need to move these elsewhere.  */
#undef	LIKE_PPC_ABI 
#define	MCORE_STRUCT_ARGS
/* RBE: end of "move elsewhere".  */

/* Run-time Target Specification.  */
#define TARGET_MCORE

/* Get tree.c to declare a target-specific specialization of
   merge_decl_attributes.  */
#define TARGET_DLLIMPORT_DECL_ATTRIBUTES 1

#define TARGET_CPU_CPP_BUILTINS()					  \
  do									  \
    {									  \
      builtin_define ("__mcore__");					  \
      builtin_define ("__MCORE__");					  \
      if (TARGET_LITTLE_END)						  \
        builtin_define ("__MCORELE__");					  \
      else								  \
        builtin_define ("__MCOREBE__");					  \
      if (TARGET_M340)							  \
        builtin_define ("__M340__");					  \
      else								  \
        builtin_define ("__M210__");					  \
    }									  \
  while (0)

/* If -m4align is ever re-enabled then add this line to the definition of CPP_SPEC
   %{!m4align:-D__MCORE_ALIGN_8__} %{m4align:-D__MCORE__ALIGN_4__}.  */
#undef  CPP_SPEC
#define CPP_SPEC "%{m210:%{mlittle-endian:%ethe m210 does not have little endian support}}"

/* We don't have a -lg library, so don't put it in the list.  */
#undef	LIB_SPEC
#define LIB_SPEC "%{!shared: %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}"

#undef	ASM_SPEC
#define	ASM_SPEC "%{mbig-endian:-EB} %{m210:-cpu=210 -EB}"

#undef  LINK_SPEC
#define LINK_SPEC "%{mbig-endian:-EB} %{m210:-EB} -X"

/* Can only count on 16 bits of availability; change to long would affect
   many architecture specific files (other architectures...).  */
extern int target_flags;

#define HARDLIT_BIT	   (1 << 0) /* Build in-line literals using 2 insns.  */
#define ALIGN8_BIT	   (1 << 1) /* Max alignment goes to 8 instead of 4.  */
#define DIV_BIT		   (1 << 2) /* Generate divide instructions.  */
#define RELAX_IMM_BIT	   (1 << 3) /* Arbitrary immediates in and, or, tst.  */
#define W_FIELD_BIT	   (1 << 4) /* Generate bit insv/extv using SImode.  */
#define	OVERALIGN_FUNC_BIT (1 << 5) /* Align functions to 4 byte boundary.  */
#define CGDATA_BIT	   (1 << 6) /* Generate callgraph data.  */
#define SLOW_BYTES_BIT     (1 << 7) /* Slow byte access.  */
#define LITTLE_END_BIT     (1 << 8) /* Generate little endian code.  */
#define M340_BIT           (1 << 9) /* Generate code for the m340.  */

#define TARGET_DEFAULT     \
 (HARDLIT_BIT | ALIGN8_BIT | DIV_BIT | RELAX_IMM_BIT | M340_BIT | LITTLE_END_BIT)

#ifndef MULTILIB_DEFAULTS
#define MULTILIB_DEFAULTS { "mlittle-endian", "m340" }
#endif

#define TARGET_HARDLIT		(target_flags & HARDLIT_BIT)
/* The ability to have 4 byte alignment is being suppressed for now.
   If this ability is reenabled, you must enable the definition below
   *and* edit t-mcore to enable multilibs for 4 byte alignment code.  */
#if 0 
#define TARGET_8ALIGN		(target_flags & ALIGN8_BIT)
#else
#define TARGET_8ALIGN		1
#endif
#define TARGET_DIV		(target_flags & DIV_BIT)
#define TARGET_RELAX_IMM        (target_flags & RELAX_IMM_BIT)
#define TARGET_W_FIELD          (target_flags & W_FIELD_BIT)
#define TARGET_OVERALIGN_FUNC   (target_flags & OVERALIGN_FUNC_BIT)
#define TARGET_CG_DATA 		(target_flags & CGDATA_BIT)
#define TARGET_CG_DATA 		(target_flags & CGDATA_BIT)
#define TARGET_SLOW_BYTES 	(target_flags & SLOW_BYTES_BIT)
#define TARGET_LITTLE_END	(target_flags & LITTLE_END_BIT)
#define TARGET_M340 		(target_flags & M340_BIT)


#define TARGET_SWITCHES							\
{ {"hardlit", 	            HARDLIT_BIT,				\
     N_("Inline constants if it can be done in 2 insns or less") },	\
  {"no-hardlit",          - HARDLIT_BIT,				\
     N_("Inline constants if it only takes 1 instruction") },		\
  {"4align",              - ALIGN8_BIT,					\
     N_("Set maximum alignment to 4") },				\
  {"8align",	            ALIGN8_BIT,					\
     N_("Set maximum alignment to 8") },				\
  {"div",                   DIV_BIT,					\
     "" },								\
  {"no-div",	          - DIV_BIT,					\
     N_("Do not use the divide instruction") },				\
  {"relax-immediates",      RELAX_IMM_BIT,				\
     "" },								\
  {"no-relax-immediates", - RELAX_IMM_BIT,				\
     N_("Do not arbitrary sized immediates in bit operations") },	\
  {"wide-bitfields",        W_FIELD_BIT,				\
     N_("Always treat bit-field as int-sized") },			\
  {"no-wide-bitfields",   - W_FIELD_BIT,				\
     "" },								\
  {"4byte-functions",       OVERALIGN_FUNC_BIT,				\
     N_("Force functions to be aligned to a 4 byte boundary") },	\
  {"no-4byte-functions",  - OVERALIGN_FUNC_BIT,				\
     N_("Force functions to be aligned to a 2 byte boundary") },	\
  {"callgraph-data",        CGDATA_BIT,					\
     N_("Emit call graph information") },				\
  {"no-callgraph-data",   - CGDATA_BIT,					\
     "" },								\
  {"slow-bytes",            SLOW_BYTES_BIT,				\
     N_("Prefer word accesses over byte accesses") },			\
  {"no-slow-bytes",       - SLOW_BYTES_BIT,				\
     "" },								\
  { "no-lsim",              0, "" },			 		\
  {"little-endian",         LITTLE_END_BIT,				\
     N_("Generate little endian code") },				\
  {"big-endian",          - LITTLE_END_BIT,				\
     "" },								\
  {"210",                 - M340_BIT,					\
     "" },								\
  {"340",                   M340_BIT,					\
     N_("Generate code for the M*Core M340") },				\
  {"",   	            TARGET_DEFAULT,				\
     "" }								\
}

extern char * mcore_current_function_name;
 
/* Target specific options (as opposed to the switches above).  */
extern const char * mcore_stack_increment_string;

#define	TARGET_OPTIONS							\
{									\
  {"stack-increment=", & mcore_stack_increment_string,			\
     N_("Maximum amount for a single stack increment operation"), 0}	\
}

/* The MCore ABI says that bitfields are unsigned by default.  */
#define CC1_SPEC "-funsigned-bitfields"

/* What options are we going to default to specific settings when
   -O* happens; the user can subsequently override these settings.
  
   Omitting the frame pointer is a very good idea on the MCore.
   Scheduling isn't worth anything on the current MCore implementation.  */
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE)	\
{						\
  if (LEVEL)					\
    {						\
      flag_no_function_cse = 1;			\
      flag_omit_frame_pointer = 1;		\
						\
      if (LEVEL >= 2)				\
        {					\
          flag_caller_saves = 0;		\
          flag_schedule_insns = 0;		\
          flag_schedule_insns_after_reload = 0;	\
        }					\
    }						\
  if (SIZE)					\
    {						\
      target_flags &= ~ HARDLIT_BIT;		\
    }						\
}

/* What options are we going to force to specific settings,
   regardless of what the user thought he wanted.
   We also use this for some post-processing of options.  */
#define OVERRIDE_OPTIONS  mcore_override_options ()

/* Target machine storage Layout.  */

#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)  	\
  if (GET_MODE_CLASS (MODE) == MODE_INT         \
      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
    {						\
      (MODE) = SImode;				\
      (UNSIGNEDP) = 1;				\
    }

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.  */
#define BITS_BIG_ENDIAN  0

/* Define this if most significant byte of a word is the lowest numbered.  */
#define BYTES_BIG_ENDIAN (! TARGET_LITTLE_END)

/* Define this if most significant word of a multiword number is the lowest
   numbered.  */
#define WORDS_BIG_ENDIAN (! TARGET_LITTLE_END)

#define LIBGCC2_WORDS_BIG_ENDIAN 1
#ifdef __MCORELE__
#undef  LIBGCC2_WORDS_BIG_ENDIAN
#define LIBGCC2_WORDS_BIG_ENDIAN 0
#endif

#define MAX_BITS_PER_WORD 32

/* Width of a word, in units (bytes).  */
#define UNITS_PER_WORD	4

/* A C expression for the size in bits of the type `long long' on the
   target machine.  If you don't define this, the default is two
   words.  */
#define LONG_LONG_TYPE_SIZE 64

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
#define PARM_BOUNDARY  	32

/* Doubles must be aligned to an 8 byte boundary.  */
#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
  ((MODE != BLKmode && (GET_MODE_SIZE (MODE) == 8)) \
   ? BIGGEST_ALIGNMENT : PARM_BOUNDARY)
     
/* Boundary (in *bits*) on which stack pointer should be aligned.  */
#define STACK_BOUNDARY  (TARGET_8ALIGN ? 64 : 32)

/* Largest increment in UNITS we allow the stack to grow in a single operation.  */
extern int mcore_stack_increment;
#define STACK_UNITS_MAXSTEP  4096

/* Allocation boundary (in *bits*) for the code of a function.  */
#define FUNCTION_BOUNDARY  ((TARGET_OVERALIGN_FUNC) ? 32 : 16)

/* Alignment of field after `int : 0' in a structure.  */
#define EMPTY_FIELD_BOUNDARY  32

/* No data type wants to be aligned rounder than this.  */
#define BIGGEST_ALIGNMENT  (TARGET_8ALIGN ? 64 : 32)

/* The best alignment to use in cases where we have a choice.  */
#define FASTEST_ALIGNMENT 32

/* Every structures size must be a multiple of 8 bits.  */
#define STRUCTURE_SIZE_BOUNDARY 8

/* Look at the fundamental type that is used for a bit-field and use 
   that to impose alignment on the enclosing structure.
   struct s {int a:8}; should have same alignment as "int", not "char".  */
#define	PCC_BITFIELD_TYPE_MATTERS	1

/* Largest integer machine mode for structures.  If undefined, the default
   is GET_MODE_SIZE(DImode).  */
#define MAX_FIXED_MODE_SIZE 32

/* Make strings word-aligned so strcpy from constants will be faster.  */
#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
  ((TREE_CODE (EXP) == STRING_CST	\
    && (ALIGN) < FASTEST_ALIGNMENT)	\
   ? FASTEST_ALIGNMENT : (ALIGN))

/* Make arrays of chars word-aligned for the same reasons.  */
#define DATA_ALIGNMENT(TYPE, ALIGN)		\
  (TREE_CODE (TYPE) == ARRAY_TYPE		\
   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
   && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
     
/* Set this nonzero if move instructions will actually fail to work
   when given unaligned data.  */
#define STRICT_ALIGNMENT 1

/* Standard register usage.  */

/* Register allocation for our first guess 

	r0		stack pointer
	r1		scratch, target reg for xtrb?
	r2-r7		arguments.
	r8-r14		call saved
	r15		link register
	ap		arg pointer (doesn't really exist, always eliminated)
	c               c bit
	fp		frame pointer (doesn't really exist, always eliminated)
	x19		two control registers.  */

/* Number of actual hardware registers.
   The hardware registers are assigned numbers for the compiler
   from 0 to just below FIRST_PSEUDO_REGISTER.
   All registers that the compiler knows about must be given numbers,
   even those that are not normally considered general registers.

   MCore has 16 integer registers and 2 control registers + the arg
   pointer.  */

#define FIRST_PSEUDO_REGISTER 20

#define R1_REG  1	/* Where literals are forced.  */
#define LK_REG	15	/* Overloaded on general register.  */
#define AP_REG  16	/* Fake arg pointer register.  */
/* RBE: mcore.md depends on CC_REG being set to 17.  */
#define CC_REG	17	/* Can't name it C_REG.  */
#define FP_REG  18	/* Fake frame pointer register.  */

/* Specify the registers used for certain standard purposes.
   The values of these macros are register numbers.  */


#undef PC_REGNUM /* Define this if the program counter is overloaded on a register.  */
#define STACK_POINTER_REGNUM 0 /* Register to use for pushing function arguments.  */
#define FRAME_POINTER_REGNUM 8 /* When we need FP, use r8.  */

/* The assembler's names for the registers.  RFP need not always be used as
   the Real framepointer; it can also be used as a normal general register.
   Note that the name `fp' is horribly misleading since `fp' is in fact only
   the argument-and-return-context pointer.  */
#define REGISTER_NAMES  				\
{				                   	\
  "sp", "r1", "r2",  "r3",  "r4",  "r5",  "r6",  "r7", 	\
  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",	\
  "apvirtual",  "c", "fpvirtual", "x19" \
}

/* 1 for registers that have pervasive standard uses
   and are not available for the register allocator.  */
#define FIXED_REGISTERS  \
 /*  r0  r1  r2  r3  r4  r5  r6  r7  r8  r9  r10 r11 r12 r13 r14 r15 ap  c  fp x19 */ \
   { 1,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  1,  1, 1, 1}

/* 1 for registers not available across function calls.
   These must include the FIXED_REGISTERS and also any
   registers that can be used without being saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   Aside from that, you can include as many other registers as you like.  */

/* RBE: r15 {link register} not available across calls,
   But we don't mark it that way here....  */
#define CALL_USED_REGISTERS \
 /*  r0  r1  r2  r3  r4  r5  r6  r7  r8  r9  r10 r11 r12 r13 r14 r15 ap  c   fp x19 */ \
   { 1,  1,  1,  1,  1,  1,  1,  1,  0,  0,  0,  0,  0,  0,  0,  0,  1,  1,  1, 1}

/* The order in which register should be allocated.  */
#define REG_ALLOC_ORDER  \
 /* r7  r6  r5  r4  r3  r2  r15 r14 r13 r12 r11 r10  r9  r8  r1  r0  ap  c   fp x19*/ \
  {  7,  6,  5,  4,  3,  2,  15, 14, 13, 12, 11, 10,  9,  8,  1,  0, 16, 17, 18, 19}

/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.
   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers.

   On the MCore regs are UNITS_PER_WORD bits wide; */
#define HARD_REGNO_NREGS(REGNO, MODE)  \
   (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
   We may keep double values in even registers.  */
#define HARD_REGNO_MODE_OK(REGNO, MODE)  \
  ((TARGET_8ALIGN && GET_MODE_SIZE (MODE) > UNITS_PER_WORD) ? (((REGNO) & 1) == 0) : (REGNO < 18))

/* Value is 1 if it is a good idea to tie two pseudo registers
   when one has mode MODE1 and one has mode MODE2.
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,