itanium2.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

(final_presence_set "2_0mm.f" "2_0m.mf")
(final_presence_set "2_0mmf." "2_0mm.f")
(final_presence_set "2_1mm.f" "2_1m.mf")
(final_presence_set "2_1mmf." "2_1mm.f")

(final_presence_set "2_0bb.b" "2_0b.bb")
(final_presence_set "2_0bbb." "2_0bb.b")
(final_presence_set "2_1bb.b" "2_1b.bb")
(final_presence_set "2_1bbb." "2_1bb.b")

(final_presence_set "2_0mb.b" "2_0m.bb")
(final_presence_set "2_0mbb." "2_0mb.b")
(final_presence_set "2_1mb.b" "2_1m.bb")
(final_presence_set "2_1mbb." "2_1mb.b")

(final_presence_set "2_0mi.b" "2_0m.ib")
(final_presence_set "2_0mib." "2_0mi.b")
(final_presence_set "2_1mi.b" "2_1m.ib")
(final_presence_set "2_1mib." "2_1mi.b")

(final_presence_set "2_0mm.b" "2_0m.mb")
(final_presence_set "2_0mmb." "2_0mm.b")
(final_presence_set "2_1mm.b" "2_1m.mb")
(final_presence_set "2_1mmb." "2_1mm.b")

(final_presence_set "2_0mf.b" "2_0m.fb")
(final_presence_set "2_0mfb." "2_0mf.b")
(final_presence_set "2_1mf.b" "2_1m.fb")
(final_presence_set "2_1mfb." "2_1mf.b")

(final_presence_set "2_0mlx." "2_0m.lx")
(final_presence_set "2_1mlx." "2_1m.lx")

;;   The following reflects the dual issue bundle types table.
;;   We could place all possible combinations here because impossible
;; combinations would go away by the subsequent constrains.
(final_presence_set
   "2_1m.lx"
   "2_0mmi.,2_0mfi.,2_0mmf.,2_0mib.,2_0mmb.,2_0mfb.,2_0mlx.")
(final_presence_set "2_1b.bb" "2_0mii.,2_0mmi.,2_0mfi.,2_0mmf.,2_0mlx.")
(final_presence_set
   "2_1m.ii,2_1m.mi,2_1m.fi,2_1m.mf,2_1m.bb,2_1m.ib,2_1m.mb,2_1m.fb"
   "2_0mii.,2_0mmi.,2_0mfi.,2_0mmf.,2_0mib.,2_0mmb.,2_0mfb.,2_0mlx.")

;;  Ports/units (nb means nop.b insn issued into given port):
(define_cpu_unit
   "2_um0, 2_um1, 2_um2, 2_um3, 2_ui0, 2_ui1, 2_uf0, 2_uf1,\
    2_ub0, 2_ub1, 2_ub2, 2_unb0, 2_unb1, 2_unb2" "two")

(exclusion_set "2_ub0" "2_unb0")
(exclusion_set "2_ub1" "2_unb1")
(exclusion_set "2_ub2" "2_unb2")

;; The following rules are used to decrease number of alternatives.
;; They are consequences of Itanium2 microarchitecture.  They also
;; describe the following rules mentioned in Itanium2
;; microarchitecture: rules mentioned in Itanium2 microarchitecture:
;; o "BBB/MBB: Always splits issue after either of these bundles".
;; o "MIB BBB: Split issue after the first bundle in this pair".
(exclusion_set
   "2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb."
   "2_1m.ii,2_1m.mi,2_1m.fi,2_1m.mf,2_1b.bb,2_1m.bb,\
    2_1m.ib,2_1m.mb,2_1m.fb,2_1m.lx")
(exclusion_set "2_0m.ib,2_0mi.b,2_0mib." "2_1b.bb")

;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the
;;; B-slot contains a nop.b or a brp instruction".
;;;   "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or
;;; nop.b, otherwise it disperses to B2".
(final_absence_set
   "2_1m.ii, 2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\
    2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx"
   "2_0mib. 2_ub2, 2_0mfb. 2_ub2, 2_0mmb. 2_ub2")

;; This is necessary to start new processor cycle when we meet stop bit.
(define_cpu_unit "2_stop" "two")
(final_absence_set
   "2_0m.ii,2_0mi.i,2_0mii.,2_0m.mi,2_0mm.i,2_0mmi.,2_0m.fi,2_0mf.i,2_0mfi.,\
    2_0m.mf,2_0mm.f,2_0mmf.,2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb.,\
    2_0m.ib,2_0mi.b,2_0mib.,2_0m.mb,2_0mm.b,2_0mmb.,2_0m.fb,2_0mf.b,2_0mfb.,\
    2_0m.lx,2_0mlx., \
    2_1m.ii,2_1mi.i,2_1mii.,2_1m.mi,2_1mm.i,2_1mmi.,2_1m.fi,2_1mf.i,2_1mfi.,\
    2_1m.mf,2_1mm.f,2_1mmf.,2_1b.bb,2_1bb.b,2_1bbb.,2_1m.bb,2_1mb.b,2_1mbb.,\
    2_1m.ib,2_1mi.b,2_1mib.,2_1m.mb,2_1mm.b,2_1mmb.,2_1m.fb,2_1mf.b,2_1mfb.,\
    2_1m.lx,2_1mlx."
   "2_stop")

;;   The issue logic can reorder M slot insns between different subtypes
;; but cannot reorder insn within the same subtypes.  The following
;; constraint is enough to describe this.
(final_presence_set "2_um1" "2_um0")
(final_presence_set "2_um3" "2_um2")

;;   The insn in the 1st I slot of the two bundle issue group will issue
;; to I0.  The second I slot insn will issue to I1.
(final_presence_set "2_ui1" "2_ui0")

;;  For exceptions of I insns:
(define_cpu_unit "2_only_ui0" "two")
(final_absence_set "2_only_ui0"  "2_ui1")

;; Insns

(define_reservation "2_M0"
  "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\
    |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\
    |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\
   +(2_um0|2_um1|2_um2|2_um3)")

(define_reservation "2_M1"
  "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
    |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\
   +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\
   +(2_um0|2_um1|2_um2|2_um3)")

(define_reservation "2_M" "2_M0|2_M1")

(define_reservation "2_M0_only_um0"
  "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\
    |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\
    |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\
   +2_um0")

(define_reservation "2_M1_only_um0"
  "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
    |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\
   +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\
   +2_um0")

(define_reservation "2_M_only_um0" "2_M0_only_um0|2_M1_only_um0")

(define_reservation "2_M0_only_um2"
  "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\
    |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\
    |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\
   +2_um2")

(define_reservation "2_M1_only_um2"
  "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
    |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\
   +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\
   +2_um2")

(define_reservation "2_M_only_um2" "2_M0_only_um2|2_M1_only_um2")

(define_reservation "2_M0_only_um23"
  "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\
    |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\
    |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\
   +(2_um2|2_um3)")

(define_reservation "2_M1_only_um23"
  "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
    |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\
   +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\
   +(2_um2|2_um3)")

(define_reservation "2_M_only_um23" "2_M0_only_um23|2_M1_only_um23")

(define_reservation "2_M0_only_um01"
  "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\
    |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\
    |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\
   +(2_um0|2_um1)")

(define_reservation "2_M1_only_um01"
  "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
    |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\
   +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\
   +(2_um0|2_um1)")

(define_reservation "2_M_only_um01" "2_M0_only_um01|2_M1_only_um01")

;; I instruction is dispersed to the lowest numbered I unit
;; not already in use.  Remember about possible splitting.
(define_reservation "2_I0"
  "2_0mi.i+2_ui0|2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0\
   |2_0mfi.+2_ui0|2_0mi.b+2_ui0|(2_1mi.i|2_1mi.b)+(2_ui0|2_ui1)\
   |(2_1mii.|2_1mmi.|2_1mfi.)+(2_ui0|2_ui1)")

(define_reservation "2_I1"
  "2_0m.ii+(2_um0|2_um1|2_um2|2_um3)+2_0mi.i+2_ui0\
   |2_0mm.i+(2_um0|2_um1|2_um2|2_um3)+2_0mmi.+2_ui0\
   |2_0mf.i+2_uf0+2_0mfi.+2_ui0\
   |2_0m.ib+(2_um0|2_um1|2_um2|2_um3)+2_0mi.b+2_ui0\
   |(2_1m.ii+2_1mi.i|2_1m.ib+2_1mi.b)+(2_um0|2_um1|2_um2|2_um3)+(2_ui0|2_ui1)\
   |2_1mm.i+(2_um0|2_um1|2_um2|2_um3)+2_1mmi.+(2_ui0|2_ui1)\
   |2_1mf.i+2_uf1+2_1mfi.+(2_ui0|2_ui1)")

(define_reservation "2_I" "2_I0|2_I1")

;; "An F slot in the 1st bundle disperses to F0".
;; "An F slot in the 2st bundle disperses to F1".
(define_reservation "2_F0"
   "2_0mf.i+2_uf0|2_0mmf.+2_uf0|2_0mf.b+2_uf0\
    |2_1mf.i+2_uf1|2_1mmf.+2_uf1|2_1mf.b+2_uf1")

(define_reservation "2_F1"
   "(2_0m.fi+2_0mf.i|2_0mm.f+2_0mmf.|2_0m.fb+2_0mf.b)\
    +(2_um0|2_um1|2_um2|2_um3)+2_uf0\
    |(2_1m.fi+2_1mf.i|2_1mm.f+2_1mmf.|2_1m.fb+2_1mf.b)\
     +(2_um0|2_um1|2_um2|2_um3)+2_uf1")

(define_reservation "2_F2"
   "(2_0m.mf+2_0mm.f+2_0mmf.+2_uf0|2_1m.mf+2_1mm.f+2_1mmf.+2_uf1)\
    +(2_um0|2_um1|2_um2|2_um3)+(2_um0|2_um1|2_um2|2_um3)\
    |(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0\
      |2_0mmf.+(2_um0|2_um1|2_um2|2_um3)\
      |2_0mib.+2_unb0|2_0mmb.+2_unb0|2_0mfb.+2_unb0)\
     +(2_1m.fi+2_1mf.i|2_1m.fb+2_1mf.b)+(2_um0|2_um1|2_um2|2_um3)+2_uf1")

(define_reservation "2_F" "2_F0|2_F1|2_F2")

;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B
;;; unit. That is, a B slot in 1st position is dispersed to B0.  In the
;;; 2nd position it is dispersed to B2".
(define_reservation "2_NB"
    "2_0b.bb+2_unb0|2_0bb.b+2_unb1|2_0bbb.+2_unb2\
     |2_0mb.b+2_unb1|2_0mbb.+2_unb2|2_0mib.+2_unb0\
     |2_0mmb.+2_unb0|2_0mfb.+2_unb0\
     |2_1b.bb+2_unb0|2_1bb.b+2_unb1
     |2_1bbb.+2_unb2|2_1mb.b+2_unb1|2_1mbb.+2_unb2\
     |2_1mib.+2_unb0|2_1mmb.+2_unb0|2_1mfb.+2_unb0")

(define_reservation "2_B0"
   "2_0b.bb+2_ub0|2_0bb.b+2_ub1|2_0bbb.+2_ub2\
    |2_0mb.b+2_ub1|2_0mbb.+2_ub2|2_0mib.+2_ub2\
    |2_0mfb.+2_ub2|2_1b.bb+2_ub0|2_1bb.b+2_ub1\
    |2_1bbb.+2_ub2|2_1mb.b+2_ub1\
    |2_1mib.+2_ub2|2_1mmb.+2_ub2|2_1mfb.+2_ub2")

(define_reservation "2_B1"
   "2_0m.bb+(2_um0|2_um1|2_um2|2_um3)+2_0mb.b+2_ub1\
    |2_0mi.b+2_ui0+2_0mib.+2_ub2\
    |2_0mm.b+(2_um0|2_um1|2_um2|2_um3)+2_0mmb.+2_ub2\
    |2_0mf.b+2_uf0+2_0mfb.+2_ub2\
    |(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0)\
     +2_1b.bb+2_ub0\
    |2_1m.bb+(2_um0|2_um1|2_um2|2_um3)+2_1mb.b+2_ub1\
    |2_1mi.b+(2_ui0|2_ui1)+2_1mib.+2_ub2\
    |2_1mm.b+(2_um0|2_um1|2_um2|2_um3)+2_1mmb.+2_ub2\
    |2_1mf.b+2_uf1+2_1mfb.+2_ub2")

(define_reservation "2_B" "2_B0|2_B1")

;; MLX bunlde uses ports equivalent to MFI bundles.

;;   For the MLI template, the I slot insn is always assigned to port I0
;; if it is in the first bundle or it is assigned to port I1 if it is in
;; the second bundle.
(define_reservation "2_L0" "2_0mlx.+2_ui0+2_uf0|2_1mlx.+2_ui1+2_uf1")

(define_reservation "2_L1"
   "2_0m.lx+(2_um0|2_um1|2_um2|2_um3)+2_0mlx.+2_ui0+2_uf0\
   |2_1m.lx+(2_um0|2_um1|2_um2|2_um3)+2_1mlx.+2_ui1+2_uf1")

(define_reservation "2_L2"
   "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
     |2_0mib.+2_unb0|2_0mmb.+2_unb0|2_0mfb.+2_unb0)
    +2_1m.lx+(2_um0|2_um1|2_um2|2_um3)+2_1mlx.+2_ui1+2_uf1")

(define_reservation "2_L" "2_L0|2_L1|2_L2")

;;   Should we describe that A insn in I slot can be issued into M
;; ports?  I think it is not necessary because of multipass
;; scheduling.  For example, the multipass scheduling could use
;; MMI-MMI instead of MII-MII where the two last I slots contain A
;; insns (even if the case is complicated by use-def conflicts).
;;
;; In any case we could describe it as
;;    (define_cpu_unit "2_ui1_0pres,2_ui1_1pres,2_ui1_2pres,2_ui1_3pres" "two")
;;    (final_presence_set "2_ui1_0pres,2_ui1_1pres,2_ui1_2pres,2_ui1_3pres"
;;                        "2_ui1")
;;    (define_reservation "b_A"
;;       "b_M|b_I\
;;        |(2_1mi.i|2_1mii.|2_1mmi.|2_1mfi.|2_1mi.b)+(2_um0|2_um1|2_um2|2_um3)\
;;         +(2_ui1_0pres|2_ui1_1pres|2_ui1_2pres|2_ui1_3pres)")

(define_reservation "2_A" "2_M|2_I")

;; We assume that there is no insn issued on the same cycle as the
;; unknown insn.
(define_cpu_unit "2_empty" "two")
(exclusion_set "2_empty"
    "2_0m.ii,2_0m.mi,2_0m.fi,2_0m.mf,2_0b.bb,2_0m.bb,2_0m.ib,2_0m.mb,2_0m.fb,\
     2_0m.lx")

(define_cpu_unit
   "2_0m_bs, 2_0mi_bs, 2_0mm_bs, 2_0mf_bs, 2_0b_bs, 2_0bb_bs, 2_0mb_bs"
   "two")
(define_cpu_unit
   "2_1m_bs, 2_1mi_bs, 2_1mm_bs, 2_1mf_bs, 2_1b_bs, 2_1bb_bs, 2_1mb_bs"
   "two")

(define_cpu_unit "2_m_cont, 2_mi_cont, 2_mm_cont, 2_mf_cont, 2_mb_cont,\
	          2_b_cont, 2_bb_cont" "two")

;; For stop in the middle of the bundles.
(define_cpu_unit "2_m_stop, 2_m0_stop, 2_m1_stop, 2_0mmi_cont" "two")
(define_cpu_unit "2_mi_stop, 2_mi0_stop, 2_mi1_stop, 2_0mii_cont" "two")

(final_presence_set "2_0m_bs"
   "2_0m.ii, 2_0m.mi, 2_0m.mf, 2_0m.fi, 2_0m.bb,\
    2_0m.ib, 2_0m.fb, 2_0m.mb, 2_0m.lx")
(final_presence_set "2_1m_bs"
   "2_1m.ii, 2_1m.mi, 2_1m.mf, 2_1m.fi, 2_1m.bb,\
    2_1m.ib, 2_1m.fb, 2_1m.mb, 2_1m.lx")
(final_presence_set "2_0mi_bs"  "2_0mi.i, 2_0mi.i")
(final_presence_set "2_1mi_bs"  "2_1mi.i, 2_1mi.i")
(final_presence_set "2_0mm_bs"  "2_0mm.i, 2_0mm.f, 2_0mm.b")
(final_presence_set "2_1mm_bs"  "2_1mm.i, 2_1mm.f, 2_1mm.b")
(final_presence_set "2_0mf_bs"  "2_0mf.i, 2_0mf.b")