frv.c

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

#undef  TARGET_ASM_FUNCTION_PROLOGUE
#define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
#undef  TARGET_ASM_FUNCTION_EPILOGUE
#define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
#undef  TARGET_ASM_INTEGER
#define TARGET_ASM_INTEGER frv_assemble_integer
#undef TARGET_INIT_BUILTINS
#define TARGET_INIT_BUILTINS frv_init_builtins
#undef TARGET_EXPAND_BUILTIN
#define TARGET_EXPAND_BUILTIN frv_expand_builtin
#undef TARGET_INIT_LIBFUNCS
#define TARGET_INIT_LIBFUNCS frv_init_libfuncs
#undef TARGET_IN_SMALL_DATA_P
#define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS frv_rtx_costs
#undef TARGET_ASM_CONSTRUCTOR
#define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
#undef TARGET_ASM_DESTRUCTOR
#define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor

#undef TARGET_ASM_OUTPUT_MI_THUNK
#define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall

#undef  TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE frv_issue_rate

#undef TARGET_FUNCTION_OK_FOR_SIBCALL
#define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
#undef TARGET_CANNOT_FORCE_CONST_MEM
#define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem

#undef TARGET_HAVE_TLS
#define TARGET_HAVE_TLS HAVE_AS_TLS

#undef TARGET_STRUCT_VALUE_RTX
#define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
#undef TARGET_MUST_PASS_IN_STACK
#define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
#undef TARGET_PASS_BY_REFERENCE
#define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
#undef TARGET_ARG_PARTIAL_BYTES
#define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes

#undef TARGET_EXPAND_BUILTIN_SAVEREGS
#define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
#undef TARGET_SETUP_INCOMING_VARARGS
#define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
#undef TARGET_MACHINE_DEPENDENT_REORG
#define TARGET_MACHINE_DEPENDENT_REORG frv_reorg

struct gcc_target targetm = TARGET_INITIALIZER;

#define FRV_SYMBOL_REF_TLS_P(RTX) \
  (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)


/* Any function call that satisfies the machine-independent
   requirements is eligible on FR-V.  */

static bool
frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
			     tree exp ATTRIBUTE_UNUSED)
{
  return true;
}

/* Return true if SYMBOL is a small data symbol and relocation RELOC
   can be used to access it directly in a load or store.  */

static FRV_INLINE bool
frv_small_data_reloc_p (rtx symbol, int reloc)
{
  return (GET_CODE (symbol) == SYMBOL_REF
	  && SYMBOL_REF_SMALL_P (symbol)
	  && (!TARGET_FDPIC || flag_pic == 1)
	  && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
}

/* Return true if X is a valid relocation unspec.  If it is, fill in UNSPEC
   appropriately.  */

static FRV_INLINE bool
frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
{
  if (GET_CODE (x) == CONST)
    {
      unspec->offset = 0;
      x = XEXP (x, 0);
      if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
	{
	  unspec->offset += INTVAL (XEXP (x, 1));
	  x = XEXP (x, 0);
	}
      if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
	{
	  unspec->symbol = XVECEXP (x, 0, 0);
	  unspec->reloc = INTVAL (XVECEXP (x, 0, 1));

	  if (unspec->offset == 0)
	    return true;

	  if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
	      && unspec->offset > 0
	      && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
	    return true;
	}
    }
  return false;
}

/* Decide whether we can force certain constants to memory.  If we
   decide we can't, the caller should be able to cope with it in
   another way.

   We never allow constants to be forced into memory for TARGET_FDPIC.
   This is necessary for several reasons:

   1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
      target-independent code will try to force them into the constant
      pool, thus leading to infinite recursion.

   2. We can never introduce new constant pool references during reload.
      Any such reference would require use of the pseudo FDPIC register.

   3. We can't represent a constant added to a function pointer (which is
      not the same as a pointer to a function+constant).

   4. In many cases, it's more efficient to calculate the constant in-line.  */

static bool
frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
{
  return TARGET_FDPIC;
}

static int
frv_default_flags_for_cpu (void)
{
  switch (frv_cpu_type)
    {
    case FRV_CPU_GENERIC:
      return MASK_DEFAULT_FRV;

    case FRV_CPU_FR550:
      return MASK_DEFAULT_FR550;

    case FRV_CPU_FR500:
    case FRV_CPU_TOMCAT:
      return MASK_DEFAULT_FR500;

    case FRV_CPU_FR450:
      return MASK_DEFAULT_FR450;

    case FRV_CPU_FR405:
    case FRV_CPU_FR400:
      return MASK_DEFAULT_FR400;

    case FRV_CPU_FR300:
    case FRV_CPU_SIMPLE:
      return MASK_DEFAULT_SIMPLE;
    }
  abort ();
}

/* Sometimes certain combinations of command options do not make
   sense on a particular target machine.  You can define a macro
   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
   defined, is executed once just after all the command options have
   been parsed.

   Don't use this macro to turn on various extra optimizations for
   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */

void
frv_override_options (void)
{
  int regno;
  unsigned int i;

  /* Set the cpu type.  */
  if (frv_cpu_string)
    {
      if (strcmp (frv_cpu_string, "simple") == 0)
	frv_cpu_type = FRV_CPU_SIMPLE;

      else if (strcmp (frv_cpu_string, "tomcat") == 0)
	frv_cpu_type = FRV_CPU_TOMCAT;

      else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0)
	error ("Unknown cpu: -mcpu=%s", frv_cpu_string);

      else
	{
	  const char *p = frv_cpu_string + sizeof ("fr") - 1;
	  if (strcmp (p, "550") == 0)
	    frv_cpu_type = FRV_CPU_FR550;

	  else if (strcmp (p, "500") == 0)
	    frv_cpu_type = FRV_CPU_FR500;

	  else if (strcmp (p, "450") == 0)
	    frv_cpu_type = FRV_CPU_FR450;

	  else if (strcmp (p, "405") == 0)
	    frv_cpu_type = FRV_CPU_FR405;

	  else if (strcmp (p, "400") == 0)
	    frv_cpu_type = FRV_CPU_FR400;

	  else if (strcmp (p, "300") == 0)
	    frv_cpu_type = FRV_CPU_FR300;

	  else if (strcmp (p, "v") == 0)
	    frv_cpu_type = FRV_CPU_GENERIC;

	  else
	    error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
	}
    }

  target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);

  /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
     linker about linking pic and non-pic code.  */
  if (TARGET_LIBPIC)
    {
      if (!flag_pic)		/* -fPIC */
	flag_pic = 2;

      if (! g_switch_set)	/* -G0 */
	{
	  g_switch_set = 1;
	  g_switch_value = 0;
	}
    }

  /* Change the branch cost value.  */
  if (frv_branch_cost_string)
    frv_branch_cost_int = atoi (frv_branch_cost_string);

  /* Change the # of insns to be converted to conditional execution.  */
  if (frv_condexec_insns_str)
    frv_condexec_insns = atoi (frv_condexec_insns_str);

  /* Change # of temporary registers used to hold integer constants.  */
  if (frv_condexec_temps_str)
    frv_condexec_temps = atoi (frv_condexec_temps_str);

  /* Change scheduling look ahead.  */
  if (frv_sched_lookahead_str)
    frv_sched_lookahead = atoi (frv_sched_lookahead_str);

  /* A C expression whose value is a register class containing hard
     register REGNO.  In general there is more than one such class;
     choose a class which is "minimal", meaning that no smaller class
     also contains the register.  */

  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
    {
      enum reg_class class;

      if (GPR_P (regno))
	{
	  int gpr_reg = regno - GPR_FIRST;

	  if (gpr_reg == GR8_REG)
	    class = GR8_REGS;

	  else if (gpr_reg == GR9_REG)
	    class = GR9_REGS;

	  else if (gpr_reg == GR14_REG)
	    class = FDPIC_FPTR_REGS;

	  else if (gpr_reg == FDPIC_REGNO)
	    class = FDPIC_REGS;

	  else if ((gpr_reg & 3) == 0)
	    class = QUAD_REGS;

	  else if ((gpr_reg & 1) == 0)
	    class = EVEN_REGS;

	  else
	    class = GPR_REGS;
	}

      else if (FPR_P (regno))
	{
	  int fpr_reg = regno - GPR_FIRST;
	  if ((fpr_reg & 3) == 0)
	    class = QUAD_FPR_REGS;

	  else if ((fpr_reg & 1) == 0)
	    class = FEVEN_REGS;

	  else
	    class = FPR_REGS;
	}

      else if (regno == LR_REGNO)
	class = LR_REG;

      else if (regno == LCR_REGNO)
	class = LCR_REG;

      else if (ICC_P (regno))
	class = ICC_REGS;

      else if (FCC_P (regno))
	class = FCC_REGS;

      else if (ICR_P (regno))
	class = ICR_REGS;

      else if (FCR_P (regno))
	class = FCR_REGS;

      else if (ACC_P (regno))
	{
	  int r = regno - ACC_FIRST;
	  if ((r & 3) == 0)
	    class = QUAD_ACC_REGS;
	  else if ((r & 1) == 0)
	    class = EVEN_ACC_REGS;
	  else
	    class = ACC_REGS;
	}

      else if (ACCG_P (regno))
	class = ACCG_REGS;

      else
	class = NO_REGS;

      regno_reg_class[regno] = class;
    }

  /* Check for small data option */
  if (!g_switch_set)
    g_switch_value = SDATA_DEFAULT_SIZE;

  /* A C expression which defines the machine-dependent operand
     constraint letters for register classes.  If CHAR is such a
     letter, the value should be the register class corresponding to
     it.  Otherwise, the value should be `NO_REGS'.  The register
     letter `r', corresponding to class `GENERAL_REGS', will not be
     passed to this macro; you do not need to handle it.

     The following letters are unavailable, due to being used as
     constraints:
	'0'..'9'
	'<', '>'
	'E', 'F', 'G', 'H'
	'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
	'Q', 'R', 'S', 'T', 'U'
	'V', 'X'
	'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */

  for (i = 0; i < 256; i++)
    reg_class_from_letter[i] = NO_REGS;

  reg_class_from_letter['a'] = ACC_REGS;
  reg_class_from_letter['b'] = EVEN_ACC_REGS;
  reg_class_from_letter['c'] = CC_REGS;
  reg_class_from_letter['d'] = GPR_REGS;
  reg_class_from_letter['e'] = EVEN_REGS;
  reg_class_from_letter['f'] = FPR_REGS;
  reg_class_from_letter['h'] = FEVEN_REGS;
  reg_class_from_letter['l'] = LR_REG;
  reg_class_from_letter['q'] = QUAD_REGS;
  reg_class_from_letter['t'] = ICC_REGS;
  reg_class_from_letter['u'] = FCC_REGS;
  reg_class_from_letter['v'] = ICR_REGS;
  reg_class_from_letter['w'] = FCR_REGS;
  reg_class_from_letter['x'] = QUAD_FPR_REGS;
  reg_class_from_letter['y'] = LCR_REG;
  reg_class_from_letter['z'] = SPR_REGS;
  reg_class_from_letter['A'] = QUAD_ACC_REGS;
  reg_class_from_letter['B'] = ACCG_REGS;