frv.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

(define_bypass 2 "fr500_m1" "fr500_m1,fr500_m2,fr500_m3,
			     fr500_m4,fr500_m5,fr500_m6")
(define_bypass 4 "fr500_m1" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
(define_insn_reservation "fr500_m1" 3
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "mnop,mlogic,maveh,msath,maddh,mqaddh"))
  "(f1|f0)")

(define_bypass 2 "fr500_m2" "fr500_m1,fr500_m2,fr500_m3,
			     fr500_m4,fr500_m5,fr500_m6")
(define_bypass 4 "fr500_m2" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
(define_insn_reservation "fr500_m2" 3
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "mrdacc,mpackh,munpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mcut,mdunpackh,mbhconve"))
  "(f1|f0) + (fr500_m2_0|fr500_m2_1)")

(define_bypass 1 "fr500_m3" "fr500_m4")
(define_insn_reservation "fr500_m3" 2
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "mclracc,mwtacc"))
  "(f1|f0) + (fr500_m3_0|fr500_m3_1)")

(define_bypass 1 "fr500_m4" "fr500_m4")
(define_insn_reservation "fr500_m4" 2
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx"))
  "(f1|f0) + (fr500_m4_0|fr500_m4_1)")

(define_bypass 2 "fr500_m5" "fr500_m1,fr500_m2,fr500_m3,
			     fr500_m4,fr500_m5,fr500_m6")
(define_bypass 4 "fr500_m5" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")
(define_insn_reservation "fr500_m5" 3
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "mdpackh"))
  "(f1|f0) + fr500_m5")

(define_bypass 1 "fr500_m6" "fr500_m4")
(define_insn_reservation "fr500_m6" 2
  (and (eq_attr "cpu" "generic,fr500,tomcat")
       (eq_attr "type" "mclracca"))
  "(f1|f0) + fr500_m6")

;; ::::::::::::::::::::
;; ::
;; :: FR400 scheduler description
;; ::
;; ::::::::::::::::::::

;; Category 2 media instructions use both media units, but can be packed
;; with non-media instructions.  Use fr400_m1unit to claim the M1 unit
;; without claiming a slot.

;; Name		Class	Units	Latency
;; ====	        =====	=====	=======
;; int		I1	I0/I1	1
;; sethi	I1	I0/I1	0       -- does not interfere with setlo
;; setlo	I1	I0/I1	1
;; mul		I1	I0	3  (*)
;; div		I1	I0	20 (*)
;; gload	I2	I0	4  (*)
;; fload	I2	I0	4       -- only 3 if read by a media insn
;; gstore	I3	I0	0       -- provides no result
;; fstore	I3	I0	0       -- provides no result
;; movfg	I4	I0	3  (*)
;; movgf	I4	I0	3  (*)
;; jumpl	I5	I0	0       -- provides no result
;;
;; (*) The results of these instructions can be read one cycle earlier
;; than indicated.  The penalty given is for instructions with write-after-
;; write dependencies.

;; The FR400 can only do loads and stores in I0, so we there's no danger
;; of memory unit collision in the same packet.  There's only one divide
;; unit too.

(define_automaton "fr400_integer")
(define_cpu_unit "fr400_mul" "fr400_integer")

(define_insn_reservation "fr400_i1_int" 1
  (and (eq_attr "cpu" "fr400,fr405,fr450")
       (eq_attr "type" "int"))
  "i1|i0")

(define_bypass 0 "fr400_i1_sethi" "fr400_i1_setlo")
(define_insn_reservation "fr400_i1_sethi" 1
  (and (eq_attr "cpu" "fr400,fr405,fr450")
       (eq_attr "type" "sethi"))
  "i1|i0")

(define_insn_reservation "fr400_i1_setlo" 1
  (and (eq_attr "cpu" "fr400,fr405,fr450")
       (eq_attr "type" "setlo"))
  "i1|i0")

;; 3 is the worst case (write-after-write hazard).
(define_insn_reservation "fr400_i1_mul" 3
  (and (eq_attr "cpu" "fr400,fr405")
       (eq_attr "type" "mul"))
  "i0 + fr400_mul")

(define_insn_reservation "fr450_i1_mul" 2
  (and (eq_attr "cpu" "fr450")
       (eq_attr "type" "mul"))
  "i0 + fr400_mul")

(define_bypass 1 "fr400_i1_macc" "fr400_i1_macc")
(define_insn_reservation "fr400_i1_macc" 2
  (and (eq_attr "cpu" "fr405,fr450")
       (eq_attr "type" "macc"))
  "(i0|i1) + fr400_mul")

(define_insn_reservation "fr400_i1_scan" 1
  (and (eq_attr "cpu" "fr400,fr405,fr450")
       (eq_attr "type" "scan"))
  "i0")

(define_insn_reservation "fr400_i1_cut" 2
  (and (eq_attr "cpu" "fr405,fr450")
       (eq_attr "type" "cut"))
  "i0 + fr400_mul")

;; 20 is for a write-after-write hazard.
(define_insn_reservation "fr400_i1_div" 20
  (and (eq_attr "cpu" "fr400,fr405")
       (eq_attr "type" "div"))
  "i0 + idiv1*19")

(define_insn_reservation "fr450_i1_div" 19
  (and (eq_attr "cpu" "fr450")
       (eq_attr "type" "div"))
  "i0 + idiv1*19")

;; 4 is for a write-after-write hazard.
(define_insn_reservation "fr400_i2" 4
  (and (eq_attr "cpu" "fr400,fr405")
       (eq_attr "type" "gload,fload"))
  "i0")

(define_insn_reservation "fr450_i2_gload" 3
  (and (eq_attr "cpu" "fr450")
       (eq_attr "type" "gload"))
  "i0")

;; 4 is for a write-after-write hazard.
(define_insn_reservation "fr450_i2_fload" 4
  (and (eq_attr "cpu" "fr450")
       (eq_attr "type" "fload"))
  "i0")

(define_insn_reservation "fr400_i3" 0
  (and (eq_attr "cpu" "fr400,fr405,fr450")
       (eq_attr "type" "gstore,fstore"))
  "i0")

;; 3 is for a write-after-write hazard.
(define_insn_reservation "fr400_i4" 3
  (and (eq_attr "cpu" "fr400,fr405")
       (eq_attr "type" "movfg,movgf"))
  "i0")

(define_insn_reservation "fr450_i4_movfg" 2
  (and (eq_attr "cpu" "fr450")
       (eq_attr "type" "movfg"))
  "i0")

;; 3 is for a write-after-write hazard.
(define_insn_reservation "fr450_i4_movgf" 3
  (and (eq_attr "cpu" "fr450")
       (eq_attr "type" "movgf"))
  "i0")

(define_insn_reservation "fr400_i5" 0
  (and (eq_attr "cpu" "fr400,fr405,fr450")
       (eq_attr "type" "jumpl"))
  "i0")

;; The bypass between FPR loads and media instructions, described above.

(define_bypass 3
  "fr400_i2"
  "fr400_m1_1,fr400_m1_2,\
   fr400_m2_1,fr400_m2_2,\
   fr400_m3_1,fr400_m3_2,\
   fr400_m4_1,fr400_m4_2,\
   fr400_m5")

;; The branch instructions all use the B unit and produce no result.

(define_insn_reservation "fr400_b" 0
  (and (eq_attr "cpu" "fr400,fr405,fr450")
       (eq_attr "type" "jump,branch,ccr,call"))
  "b0")

;; FP->FP moves are marked as "fsconv" instructions in the define_insns
;; below, but are implemented on the FR400 using "mlogic" instructions.
;; It's easier to class "fsconv" as a "m1:1" instruction than provide
;; separate define_insns for the FR400.

;; M1 instructions store their results in FPRs.  Any instruction can read
;; the result in the following cycle, so no penalty occurs.

(define_automaton "fr400_media")
(define_cpu_unit "fr400_m1a,fr400_m1b,fr400_m2a" "fr400_media")
(exclusion_set "fr400_m1a,fr400_m1b" "fr400_m2a")

(define_reservation "fr400_m1" "(f1|f0) + (fr400_m1a|fr400_m1b)")
(define_reservation "fr400_m2" "f0 + fr400_m2a")

(define_insn_reservation "fr400_m1_1" 1
  (and (eq_attr "cpu" "fr400,fr405")
       (eq_attr "type" "fsconv,mnop,mlogic,maveh,msath,maddh,mabsh,mset"))
  "fr400_m1")

(define_insn_reservation "fr400_m1_2" 1
  (and (eq_attr "cpu" "fr400,fr405")
       (eq_attr "type" "mqaddh,mqsath,mqlimh,mqshift"))
  "fr400_m2")

;; M2 instructions store their results in accumulators, which are read
;; by M2 or M4 media commands.  M2 instructions can read the results in
;; the following cycle, but M4 instructions must wait a cycle more.

(define_bypass 1
  "fr400_m2_1,fr400_m2_2"
  "fr400_m2_1,fr400_m2_2")

(define_insn_reservation "fr400_m2_1" 2
  (and (eq_attr "cpu" "fr400,fr405")
       (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mcpx,maddacc"))
  "fr400_m1")

(define_insn_reservation "fr400_m2_2" 2
  (and (eq_attr "cpu" "fr400,fr405")
       (eq_attr "type" "mqmulh,mqmulxh,mqmach,mqcpx,mdaddacc"))
  "fr400_m2")

;; For our purposes, there seems to be little real difference between
;; M1 and M3 instructions.  Keep them separate anyway in case the distinction
;; is needed later.

(define_insn_reservation "fr400_m3_1" 1
  (and (eq_attr "cpu" "fr400,fr405")
       (eq_attr "type" "mpackh,mrot,mshift,mexpdhw"))
  "fr400_m1")

(define_insn_reservation "fr400_m3_2" 1
  (and (eq_attr "cpu" "fr400,fr405")
       (eq_attr "type" "munpackh,mdpackh,mbhconv,mexpdhd,mwcut,mdrot,mcpl"))
  "fr400_m2")

;; M4 instructions write to accumulators or FPRs.  MOVFG and STF
;; instructions can read an FPR result in the following cycle, but
;; M-unit instructions must wait a cycle more for either kind of result.

(define_bypass 1 "fr400_m4_1,fr400_m4_2" "fr400_i3,fr400_i4")

(define_insn_reservation "fr400_m4_1" 2
  (and (eq_attr "cpu" "fr400,fr405")
       (eq_attr "type" "mrdacc,mcut,mclracc"))
  "fr400_m1")

(define_insn_reservation "fr400_m4_2" 2
  (and (eq_attr "cpu" "fr400,fr405")
       (eq_attr "type" "mclracca,mdcut"))
  "fr400_m2")

;; M5 instructions always incur a 1-cycle penalty.

(define_insn_reservation "fr400_m5" 2
  (and (eq_attr "cpu" "fr400,fr405")
       (eq_attr "type" "mwtacc"))
  "fr400_m2")

;; ::::::::::::::::::::
;; ::
;; :: FR450 media scheduler description
;; ::
;; ::::::::::::::::::::

;; The FR451 media restrictions are similar to the FR400's, but not as
;; strict and not as regular.  There are 6 categories with the following
;; restrictions:
;;
;;		          M1
;;	      M-1  M-2  M-3  M-4  M-5  M-6
;;	M-1:         x         x         x
;;	M-2:    x    x    x    x    x    x
;;  M0	M-3:         x         x         x
;;	M-4:    x    x    x    x
;;	M-5:         x         x         x
;;	M-6:    x    x    x    x    x    x
;;
;; where "x" indicates a conflict.
;;
;; There is no difference between M-1 and M-3 as far as issue
;; restrictions are concerned, so they are combined as "m13".

;; Units for odd-numbered categories.  There can be two of these
;; in a packet.
(define_cpu_unit "fr450_m13a,fr450_m13b" "float_media")
(define_cpu_unit "fr450_m5a,fr450_m5b" "float_media")

;; Units for even-numbered categories.  There can only be one per packet.
(define_cpu_unit "fr450_m2a,fr450_m4a,fr450_m6a" "float_media")

;; Enforce the restriction matrix above.
(exclusion_set "fr450_m2a,fr450_m4a,fr450_m6a" "fr450_m13a,fr450_m13b")
(exclusion_set "fr450_m2a,fr450_m6a" "fr450_m5a,fr450_m5b")
(exclusion_set "fr450_m4a,fr450_m6a" "fr450_m2a")

(define_reservation "fr450_m13" "(f1|f0) + (fr450_m13a|fr450_m13b)")
(define_reservation "fr450_m2" "f0 + fr450_m2a")
(define_reservation "fr450_m4" "f0 + fr450_m4a")
(define_reservation "fr450_m5" "(f1|f0) + (fr450_m5a|fr450_m5b)")
(define_reservation "fr450_m6" "(f0|f1) + fr450_m6a")

;; MD-1, MD-3 and MD-8 instructions, which are the same as far
;; as scheduling is concerned.  The inputs and outputs are FPRs.
;; Instructions that have 32-bit inputs and outputs belong to M-1 while
;; the rest belong to M-2.
;;
;; ??? Arithmetic shifts (MD-6) have an extra cycle latency, but we don't
;; make the distinction between them and logical shifts.
(define_insn_reservation "fr450_md138_1" 1
  (and (eq_attr "cpu" "fr450")
       (eq_attr "type" "fsconv,mnop,mlogic,maveh,msath,maddh,mabsh,mset,
			mrot,mshift,mexpdhw,mpackh"))
  "fr450_m13")

(define_insn_reservation "fr450_md138_2" 1
  (and (eq_attr "cpu" "fr450")
       (eq_attr "type" "mqaddh,mqsath,mqlimh,
			mdrot,mwcut,mqshift,mexpdhd,
			munpackh,mdpackh,mbhconv,mcpl"))
  "fr450_m2")

;; MD-2 instructions.  These take FPR or ACC inputs and produce an ACC output.
;; Instructions that write to double ACCs belong to M-3 while those that write
;; to quad ACCs belong to M-4.
(define_insn_reservation "fr450_md2_3" 2
  (and (eq_attr "cpu" "fr450")
       (eq_attr "type" "mmulh,mmach,mcpx,mmulxh,mmrdh,maddacc"))
  "fr450_m13")

(define_insn_reservation "fr450_md2_4" 2
  (and (eq_attr "cpu" "fr450")