mips-ps-3d.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

	(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
		      (match_operand:V2SF 2 "register_operand" "f")]
		     UNSPEC_ADDR_PS))]
  "TARGET_MIPS3D"
  "addr.ps\t%0,%1,%2"
  [(set_attr "type" "fadd")
   (set_attr "mode" "SF")])

; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word
(define_insn "mips_cvt_pw_ps"
  [(set (match_operand:V2SF 0 "register_operand" "=f")
	(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
		     UNSPEC_CVT_PW_PS))]
  "TARGET_MIPS3D"
  "cvt.pw.ps\t%0,%1"
  [(set_attr "type" "fcvt")
   (set_attr "mode" "SF")])

; cvt.ps.pw - Floating Point Convert Paired Word to Paired Single
(define_insn "mips_cvt_ps_pw"
  [(set (match_operand:V2SF 0 "register_operand" "=f")
	(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
		     UNSPEC_CVT_PS_PW))]
  "TARGET_MIPS3D"
  "cvt.ps.pw\t%0,%1"
  [(set_attr "type" "fcvt")
   (set_attr "mode" "SF")])

; mulr.ps - Floating Point Reduction Multiply
(define_insn "mips_mulr_ps"
  [(set (match_operand:V2SF 0 "register_operand" "=f")
	(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
		      (match_operand:V2SF 2 "register_operand" "f")]
		     UNSPEC_MULR_PS))]
  "TARGET_MIPS3D"
  "mulr.ps\t%0,%1,%2"
  [(set_attr "type" "fmul")
   (set_attr "mode" "SF")])

;----------------------------------------------------------------------------
; Floating Point Comparisons for Scalars
;----------------------------------------------------------------------------

(define_insn "mips_cabs_cond_<fmt>"
  [(set (match_operand:CC 0 "register_operand" "=z")
	(unspec:CC [(match_operand:SCALARF 1 "register_operand" "f")
		    (match_operand:SCALARF 2 "register_operand" "f")
		    (match_operand 3 "const_int_operand" "")]
		   UNSPEC_CABS))]
  "TARGET_MIPS3D"
  "cabs.%Y3.<fmt>\t%0,%1,%2"
  [(set_attr "type" "fcmp")
   (set_attr "mode" "FPSW")])


;----------------------------------------------------------------------------
; Floating Point Comparisons for Four Singles
;----------------------------------------------------------------------------

(define_insn_and_split "mips_c_cond_4s"
  [(set (match_operand:CCV4 0 "register_operand" "=z")
	(unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f")
		      (match_operand:V2SF 2 "register_operand" "f")
		      (match_operand:V2SF 3 "register_operand" "f")
		      (match_operand:V2SF 4 "register_operand" "f")
		      (match_operand 5 "const_int_operand" "")]
		     UNSPEC_C))]
  "TARGET_PAIRED_SINGLE_FLOAT"
  "#"
  "&& reload_completed"
  [(set (match_dup 6)
	(unspec:CCV2 [(match_dup 1)
		      (match_dup 2)
		      (match_dup 5)]
		     UNSPEC_C))
   (set (match_dup 7)
	(unspec:CCV2 [(match_dup 3)
		      (match_dup 4)
		      (match_dup 5)]
		     UNSPEC_C))]
{
  operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0);
  operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8);
}
  [(set_attr "type" "fcmp")
   (set_attr "length" "8")
   (set_attr "mode" "FPSW")])

(define_insn_and_split "mips_cabs_cond_4s"
  [(set (match_operand:CCV4 0 "register_operand" "=z")
	(unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f")
		      (match_operand:V2SF 2 "register_operand" "f")
		      (match_operand:V2SF 3 "register_operand" "f")
		      (match_operand:V2SF 4 "register_operand" "f")
		      (match_operand 5 "const_int_operand" "")]
		     UNSPEC_CABS))]
  "TARGET_MIPS3D"
  "#"
  "&& reload_completed"
  [(set (match_dup 6)
	(unspec:CCV2 [(match_dup 1)
		      (match_dup 2)
		      (match_dup 5)]
		     UNSPEC_CABS))
   (set (match_dup 7)
	(unspec:CCV2 [(match_dup 3)
		      (match_dup 4)
		      (match_dup 5)]
		     UNSPEC_CABS))]
{
  operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0);
  operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8);
}
  [(set_attr "type" "fcmp")
   (set_attr "length" "8")
   (set_attr "mode" "FPSW")])


;----------------------------------------------------------------------------
; Floating Point Comparisons for Paired Singles
;----------------------------------------------------------------------------

(define_insn "mips_c_cond_ps"
  [(set (match_operand:CCV2 0 "register_operand" "=z")
	(unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f")
		      (match_operand:V2SF 2 "register_operand" "f")
		      (match_operand 3 "const_int_operand" "")]
		     UNSPEC_C))]
  "TARGET_PAIRED_SINGLE_FLOAT"
  "c.%Y3.ps\t%0,%1,%2"
  [(set_attr "type" "fcmp")
   (set_attr "mode" "FPSW")])

(define_insn "mips_cabs_cond_ps"
  [(set (match_operand:CCV2 0 "register_operand" "=z")
	(unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f")
		      (match_operand:V2SF 2 "register_operand" "f")
		      (match_operand 3 "const_int_operand" "")]
		     UNSPEC_CABS))]
  "TARGET_MIPS3D"
  "cabs.%Y3.ps\t%0,%1,%2"
  [(set_attr "type" "fcmp")
   (set_attr "mode" "FPSW")])


;----------------------------------------------------------------------------
; Floating Point Branch Instructions.
;----------------------------------------------------------------------------

; Branch on Any of Four Floating Point Condition Codes True
(define_insn "bc1any4t"
  [(set (pc)
	(if_then_else (ne:CCV4 (match_operand:CCV4 0 "register_operand" "z")
			       (const_int 0))
		      (label_ref (match_operand 1 "" ""))
		      (pc)))]
  "TARGET_MIPS3D"
  "%*bc1any4t\t%0,%1%/"
  [(set_attr "type" "branch")
   (set_attr "mode" "none")])

; Branch on Any of Four Floating Point Condition Codes False
(define_insn "bc1any4f"
  [(set (pc)
	(if_then_else (ne:CCV4 (match_operand:CCV4 0 "register_operand" "z")
			       (const_int -1))
		      (label_ref (match_operand 1 "" ""))
		      (pc)))]
  "TARGET_MIPS3D"
  "%*bc1any4f\t%0,%1%/"
  [(set_attr "type" "branch")
   (set_attr "mode" "none")])

; Branch on Any of Two Floating Point Condition Codes True
(define_insn "bc1any2t"
  [(set (pc)
	(if_then_else (ne:CCV2 (match_operand:CCV2 0 "register_operand" "z")
			       (const_int 0))
		      (label_ref (match_operand 1 "" ""))
		      (pc)))]
  "TARGET_MIPS3D"
  "%*bc1any2t\t%0,%1%/"
  [(set_attr "type" "branch")
   (set_attr "mode" "none")])

; Branch on Any of Two Floating Point Condition Codes False
(define_insn "bc1any2f"
  [(set (pc)
	(if_then_else (ne:CCV2 (match_operand:CCV2 0 "register_operand" "z")
			       (const_int -1))
		      (label_ref (match_operand 1 "" ""))
		      (pc)))]
  "TARGET_MIPS3D"
  "%*bc1any2f\t%0,%1%/"
  [(set_attr "type" "branch")
   (set_attr "mode" "none")])

;----------------------------------------------------------------------------
; Floating Point Reduced Precision Reciprocal Square Root Instructions.
;----------------------------------------------------------------------------

(define_insn "mips_rsqrt1_<fmt>"
  [(set (match_operand:ANYF 0 "register_operand" "=f")
	(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
		     UNSPEC_RSQRT1))]
  "TARGET_MIPS3D"
  "rsqrt1.<fmt>\t%0,%1"
  [(set_attr "type" "frsqrt1")
   (set_attr "mode" "<UNITMODE>")])

(define_insn "mips_rsqrt2_<fmt>"
  [(set (match_operand:ANYF 0 "register_operand" "=f")
	(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
		      (match_operand:ANYF 2 "register_operand" "f")]
		     UNSPEC_RSQRT2))]
  "TARGET_MIPS3D"
  "rsqrt2.<fmt>\t%0,%1,%2"
  [(set_attr "type" "frsqrt2")
   (set_attr "mode" "<UNITMODE>")])

(define_insn "mips_recip1_<fmt>"
  [(set (match_operand:ANYF 0 "register_operand" "=f")
	(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
		     UNSPEC_RECIP1))]
  "TARGET_MIPS3D"
  "recip1.<fmt>\t%0,%1"
  [(set_attr "type" "frdiv1")
   (set_attr "mode" "<UNITMODE>")])

(define_insn "mips_recip2_<fmt>"
  [(set (match_operand:ANYF 0 "register_operand" "=f")
	(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
		      (match_operand:ANYF 2 "register_operand" "f")]
		     UNSPEC_RECIP2))]
  "TARGET_MIPS3D"
  "recip2.<fmt>\t%0,%1,%2"
  [(set_attr "type" "frdiv2")
   (set_attr "mode" "<UNITMODE>")])