mips-ps-3d.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

;; MIPS Paired-Single Floating and MIPS-3D Instructions.
;; Copyright (C) 2004 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.

(define_insn "*movcc_v2sf_<mode>"
  [(set (match_operand:V2SF 0 "register_operand" "=f,f")
	(if_then_else:V2SF
	 (match_operator:GPR 4 "equality_operator"
			 [(match_operand:GPR 1 "register_operand" "d,d")
			  (const_int 0)])
	 (match_operand:V2SF 2 "register_operand" "f,0")
	 (match_operand:V2SF 3 "register_operand" "0,f")))]
  "TARGET_PAIRED_SINGLE_FLOAT"
  "@
    mov%T4.ps\t%0,%2,%1
    mov%t4.ps\t%0,%3,%1"
  [(set_attr "type" "condmove")
   (set_attr "mode" "SF")])

(define_insn "mips_cond_move_tf_ps"
  [(set (match_operand:V2SF 0 "register_operand" "=f,f")
	(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f,0")
		      (match_operand:V2SF 2 "register_operand" "0,f")
		      (match_operand:CCV2 3 "register_operand" "z,z")]
		     UNSPEC_MOVE_TF_PS))]
  "TARGET_PAIRED_SINGLE_FLOAT"
  "@
    movt.ps\t%0,%1,%3
    movf.ps\t%0,%2,%3"
  [(set_attr "type" "condmove")
   (set_attr "mode" "SF")])

(define_expand "movv2sfcc"
  [(set (match_dup 4) (match_operand 1 "comparison_operator"))
   (set (match_operand:V2SF 0 "register_operand")
	(if_then_else:V2SF (match_dup 5)
			   (match_operand:V2SF 2 "register_operand")
			   (match_operand:V2SF 3 "register_operand")))]
  "TARGET_PAIRED_SINGLE_FLOAT"
{
  /* We can only support MOVN.PS and MOVZ.PS.
     NOTE: MOVT.PS and MOVF.PS have different semantics from MOVN.PS and 
	   MOVZ.PS.  MOVT.PS and MOVF.PS depend on two CC values and move 
	   each item independently.  */

  if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
    FAIL;

  gen_conditional_move (operands);
  DONE;
})

; pul.ps - Pair Upper Lower
(define_insn "mips_pul_ps"
  [(set (match_operand:V2SF 0 "register_operand" "=f")
	(vec_merge:V2SF
	 (match_operand:V2SF 1 "register_operand" "f")
	 (match_operand:V2SF 2 "register_operand" "f")
	 (const_int 2)))]
  "TARGET_PAIRED_SINGLE_FLOAT"
  "pul.ps\t%0,%1,%2"
  [(set_attr "type" "fmove")
   (set_attr "mode" "SF")])

; puu.ps - Pair upper upper
(define_insn "mips_puu_ps"
  [(set (match_operand:V2SF 0 "register_operand" "=f")
	(vec_merge:V2SF
	 (match_operand:V2SF 1 "register_operand" "f")
	 (vec_select:V2SF (match_operand:V2SF 2 "register_operand" "f")
			  (parallel [(const_int 1)
				     (const_int 0)]))
	 (const_int 2)))]
  "TARGET_PAIRED_SINGLE_FLOAT"
  "puu.ps\t%0,%1,%2"
  [(set_attr "type" "fmove")
   (set_attr "mode" "SF")])

; pll.ps - Pair Lower Lower
(define_insn "mips_pll_ps"
  [(set (match_operand:V2SF 0 "register_operand" "=f")
	(vec_merge:V2SF
	 (vec_select:V2SF (match_operand:V2SF 1 "register_operand" "f")
			  (parallel [(const_int 1)
				     (const_int 0)]))
	 (match_operand:V2SF 2 "register_operand" "f")
	 (const_int 2)))]
  "TARGET_PAIRED_SINGLE_FLOAT"
  "pll.ps\t%0,%1,%2"
  [(set_attr "type" "fmove")
   (set_attr "mode" "SF")])

; plu.ps - Pair Lower Upper
(define_insn "mips_plu_ps"
  [(set (match_operand:V2SF 0 "register_operand" "=f")
	(vec_merge:V2SF
	 (vec_select:V2SF (match_operand:V2SF 1 "register_operand" "f")
			  (parallel [(const_int 1)
				     (const_int 0)]))
	 (vec_select:V2SF (match_operand:V2SF 2 "register_operand" "f")
			  (parallel [(const_int 1)
				     (const_int 0)]))
	 (const_int 2)))]
  "TARGET_PAIRED_SINGLE_FLOAT"
  "plu.ps\t%0,%1,%2"
  [(set_attr "type" "fmove")
   (set_attr "mode" "SF")])

; vec_init
(define_expand "vec_initv2sf"
  [(match_operand:V2SF 0 "register_operand")
   (match_operand:V2SF 1 "")]
  "TARGET_PAIRED_SINGLE_FLOAT"
{
  rtx op0 = force_reg (SFmode, XVECEXP (operands[1], 0, 0));
  rtx op1 = force_reg (SFmode, XVECEXP (operands[1], 0, 1));
  emit_insn (gen_vec_initv2sf_internal (operands[0], op0, op1));
  DONE;
})

(define_insn "vec_initv2sf_internal"
  [(set (match_operand:V2SF 0 "register_operand" "=f")
	(vec_concat:V2SF
	 (match_operand:SF 1 "register_operand" "f")
	 (match_operand:SF 2 "register_operand" "f")))]
  "TARGET_PAIRED_SINGLE_FLOAT"
{
  if (BYTES_BIG_ENDIAN)
    return "cvt.ps.s\t%0,%1,%2";
  else
    return "cvt.ps.s\t%0,%2,%1";
}
  [(set_attr "type" "fcvt")
   (set_attr "mode" "SF")])

;; ??? This is only generated if we perform a vector operation that has to be
;; emulated.  There is no other way to get a vector mode bitfield extract
;; currently.

(define_insn "vec_extractv2sf"
  [(set (match_operand:SF 0 "register_operand" "=f")
	(vec_select:SF (match_operand:V2SF 1 "register_operand" "f")
		       (parallel
			[(match_operand 2 "const_0_or_1_operand" "")])))]
  "TARGET_PAIRED_SINGLE_FLOAT"
{
  if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN)
    return "cvt.s.pu\t%0,%1";
  else
    return "cvt.s.pl\t%0,%1";
}
  [(set_attr "type" "fcvt")
   (set_attr "mode" "SF")])

;; ??? This is only generated if we disable the vec_init pattern.  There is
;; no other way to get a vector mode bitfield store currently.

(define_expand "vec_setv2sf"
  [(match_operand:V2SF 0 "register_operand")
   (match_operand:SF 1 "register_operand")
   (match_operand 2 "const_0_or_1_operand")]
  "TARGET_PAIRED_SINGLE_FLOAT"
{
  rtx temp;

  /* We don't have an insert instruction, so we duplicate the float, and
     then use a PUL instruction.  */
  temp = gen_reg_rtx (V2SFmode);
  emit_insn (gen_mips_cvt_ps_s (temp, operands[1], operands[1]));
  if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN)
    emit_insn (gen_mips_pul_ps (operands[0], temp, operands[0]));
  else
    emit_insn (gen_mips_pul_ps (operands[0], operands[0], temp));
  DONE;
})

; cvt.ps.s - Floating Point Convert Pair to Paired Single
(define_expand "mips_cvt_ps_s"
  [(match_operand:V2SF 0 "register_operand")
   (match_operand:SF 1 "register_operand")
   (match_operand:SF 2 "register_operand")]
  "TARGET_PAIRED_SINGLE_FLOAT"
{
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_vec_initv2sf_internal (operands[0], operands[1],
	       operands[2]));
  else
    emit_insn (gen_vec_initv2sf_internal (operands[0], operands[2],
	       operands[1]));
  DONE;
})

; cvt.s.pl - Floating Point Convert Pair Lower to Single Floating Point
(define_expand "mips_cvt_s_pl"
  [(set (match_operand:SF 0 "register_operand")
	(vec_select:SF (match_operand:V2SF 1 "register_operand")
		       (parallel [(match_dup 2)])))]
  "TARGET_PAIRED_SINGLE_FLOAT"
  { operands[2] = GEN_INT (BYTES_BIG_ENDIAN); })

; cvt.s.pu - Floating Point Convert Pair Upper to Single Floating Point
(define_expand "mips_cvt_s_pu"
  [(set (match_operand:SF 0 "register_operand")
	(vec_select:SF (match_operand:V2SF 1 "register_operand")
		       (parallel [(match_dup 2)])))]
  "TARGET_PAIRED_SINGLE_FLOAT"
  { operands[2] = GEN_INT (!BYTES_BIG_ENDIAN); })

; alnv.ps - Floating Point Align Variable
(define_insn "mips_alnv_ps"
  [(set (match_operand:V2SF 0 "register_operand" "=f")
	(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
		      (match_operand:V2SF 2 "register_operand" "f")
		      (match_operand:SI 3 "register_operand" "d")]
		     UNSPEC_ALNV_PS))]
  "TARGET_PAIRED_SINGLE_FLOAT"
  "alnv.ps\t%0,%1,%2,%3"
  [(set_attr "type" "fmove")
   (set_attr "mode" "SF")])

; addr.ps - Floating Point Reduction Add
(define_insn "mips_addr_ps"
  [(set (match_operand:V2SF 0 "register_operand" "=f")