sb1.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

       (and (eq_attr "type" "mfhilo")
	    (match_operand 1 "lo_operand")))
  "sb1_ex1")

;; mt{hi,lo} to mul/div is 4 cycles.

(define_insn_reservation "ir_sb1_mthilo" 4
  (and (eq_attr "cpu" "sb1")
       (eq_attr "type" "mthilo"))
  "sb1_ex1")

;; mt{hi,lo} to mf{hi,lo} is 3 cycles.

(define_bypass 3 "ir_sb1_mthilo" "ir_sb1_mfhi,ir_sb1_mflo")

;; multiply latency to an EX operation is 3 cycles.

;; ??? Should check whether we need to make multiply conflict with moves
;; to/from hilo registers.

(define_insn_reservation "ir_sb1_mulsi" 3
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "imul,imadd")
	    (eq_attr "mode" "SI")))
  "sb1_ex1+sb1_mul")

;; muldi to mfhi is 4 cycles.
;; Blocks any other multiply insn issue for 1 cycle.

(define_insn_reservation "ir_sb1_muldi" 4
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "imul")
	    (eq_attr "mode" "DI")))
  "sb1_ex1+sb1_mul, sb1_mul")

;; muldi to mflo is 3 cycles.

(define_bypass 3 "ir_sb1_muldi" "ir_sb1_mflo")

;;  mul latency is 7 cycles if the result is used by any LS insn.

;; This assumes that if a load is dependent on a previous insn, then it must
;; be an address dependence.

(define_bypass 7
  "ir_sb1_mulsi,ir_sb1_muldi"
  "ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload,
   ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")

(define_bypass 7
  "ir_sb1_mulsi,ir_sb1_muldi"
  "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
  "store_data_bypass_p")

;; The divide unit is not pipelined.  Divide busy is asserted in the 4th
;; cycle, and then deasserted on the latency cycle.  So only one divide at
;; a time, but the first/last 4 cycles can overlap.

;; ??? All divides block writes to hi/lo regs.  hi/lo regs are written 4 cycles
;; after the latency cycle for divides (e.g. 40/72).  dmult writes lo in
;; cycle 7, and hi in cycle 8.  All other insns write hi/lo regs in cycle 7.
;; Default for output dependencies is the difference in latencies, which is
;; only 1 cycle off here, e.g. div to mtlo stalls for 32 cycles, but should
;; stall for 33 cycles.  This does not seem significant enough to worry about.

(define_insn_reservation "ir_sb1_divsi" 36
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "idiv")
	    (eq_attr "mode" "SI")))
  "sb1_ex1, nothing*3, sb1_div*32")

(define_insn_reservation "ir_sb1_divdi" 68
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "idiv")
	    (eq_attr "mode" "DI")))
  "sb1_ex1, nothing*3, sb1_div*64")

(define_insn_reservation "ir_sb1_fpu_2pipes" 4
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1")
	    (eq_attr "sb1_fp_pipes" "two")))
  "sb1_fp1 | sb1_fp0")

(define_insn_reservation "ir_sb1_fpu_1pipe" 4
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1")
	    (eq_attr "sb1_fp_pipes" "one")))
  "sb1_fp1")

(define_insn_reservation "ir_sb1_fpu_step2_2pipes" 8
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "frdiv2,frsqrt2")
	    (eq_attr "sb1_fp_pipes" "two")))
  "sb1_fp1 | sb1_fp0")

(define_insn_reservation "ir_sb1_fpu_step2_1pipe" 8
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "frdiv2,frsqrt2")
	    (eq_attr "sb1_fp_pipes" "one")))
  "sb1_fp1")

;; ??? madd/msub 4-cycle latency to itself (same fr?), but 8 cycle latency
;; otherwise.

;; ??? Blocks issue of another non-madd/msub after 4 cycles.

(define_insn_reservation "ir_sb1_fmadd_2pipes" 8
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "fmadd")
	    (eq_attr "sb1_fp_pipes" "two")))
  "sb1_fp1 | sb1_fp0")

(define_insn_reservation "ir_sb1_fmadd_1pipe" 8
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "fmadd")
	    (eq_attr "sb1_fp_pipes" "one")))
  "sb1_fp1")

(define_insn_reservation "ir_sb1_fcmp" 4
  (and (eq_attr "cpu" "sb1")
       (eq_attr "type" "fcmp"))
  "sb1_fp1")

;; mtc1 latency 5 cycles.

(define_insn_reservation "ir_sb1_mtxfer" 5
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "xfer")
	    (match_operand 0 "fpr_operand")))
  "sb1_fp0")

;; mfc1 latency 1 cycle.  

(define_insn_reservation "ir_sb1_mfxfer" 1
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "xfer")
	    (not (match_operand 0 "fpr_operand"))))
  "sb1_fp0")

;; ??? Can deliver at most 1 result per every 6 cycles because of issue
;; restrictions.

(define_insn_reservation "ir_sb1_divsf_2pipes" 24
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "fdiv")
	    (and (eq_attr "mode" "SF")
		 (eq_attr "sb1_fp_pipes" "two"))))
  "sb1_fp1 | sb1_fp0")

(define_insn_reservation "ir_sb1_divsf_1pipe" 24
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "fdiv")
	    (and (eq_attr "mode" "SF")
		 (eq_attr "sb1_fp_pipes" "one"))))
  "sb1_fp1")

;; ??? Can deliver at most 1 result per every 8 cycles because of issue
;; restrictions.

(define_insn_reservation "ir_sb1_divdf_2pipes" 32
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "fdiv")
	    (and (eq_attr "mode" "DF")
		 (eq_attr "sb1_fp_pipes" "two"))))
  "sb1_fp1 | sb1_fp0")

(define_insn_reservation "ir_sb1_divdf_1pipe" 32
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "fdiv")
	    (and (eq_attr "mode" "DF")
		 (eq_attr "sb1_fp_pipes" "one"))))
  "sb1_fp1")

;; ??? Can deliver at most 1 result per every 3 cycles because of issue
;; restrictions.

(define_insn_reservation "ir_sb1_recipsf_2pipes" 12
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "frdiv")
	    (and (eq_attr "mode" "SF")
		 (eq_attr "sb1_fp_pipes" "two"))))
  "sb1_fp1 | sb1_fp0")

(define_insn_reservation "ir_sb1_recipsf_1pipe" 12
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "frdiv")
	    (and (eq_attr "mode" "SF")
		 (eq_attr "sb1_fp_pipes" "one"))))
  "sb1_fp1")

;; ??? Can deliver at most 1 result per every 5 cycles because of issue
;; restrictions.

(define_insn_reservation "ir_sb1_recipdf_2pipes" 20
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "frdiv")
	    (and (eq_attr "mode" "DF")
		 (eq_attr "sb1_fp_pipes" "two"))))
  "sb1_fp1 | sb1_fp0")

(define_insn_reservation "ir_sb1_recipdf_1pipe" 20
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "frdiv")
	    (and (eq_attr "mode" "DF")
		 (eq_attr "sb1_fp_pipes" "one"))))
  "sb1_fp1")

;; ??? Can deliver at most 1 result per every 7 cycles because of issue
;; restrictions.

(define_insn_reservation "ir_sb1_sqrtsf_2pipes" 28
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "fsqrt")
	    (and (eq_attr "mode" "SF")
		 (eq_attr "sb1_fp_pipes" "two"))))
  "sb1_fp1 | sb1_fp0")

(define_insn_reservation "ir_sb1_sqrtsf_1pipe" 28
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "fsqrt")
	    (and (eq_attr "mode" "SF")
		 (eq_attr "sb1_fp_pipes" "one"))))
  "sb1_fp1")

;; ??? Can deliver at most 1 result per every 10 cycles because of issue
;; restrictions.

(define_insn_reservation "ir_sb1_sqrtdf_2pipes" 40
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "fsqrt")
	    (and (eq_attr "mode" "DF")
		 (eq_attr "sb1_fp_pipes" "two"))))
  "sb1_fp1 | sb1_fp0")

(define_insn_reservation "ir_sb1_sqrtdf_1pipe" 40
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "fsqrt")
	    (and (eq_attr "mode" "DF")
		 (eq_attr "sb1_fp_pipes" "one"))))
  "sb1_fp1")

;; ??? Can deliver at most 1 result per every 4 cycles because of issue
;; restrictions.

(define_insn_reservation "ir_sb1_rsqrtsf_2pipes" 16
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "frsqrt")
	    (and (eq_attr "mode" "SF")
		 (eq_attr "sb1_fp_pipes" "two"))))
  "sb1_fp1 | sb1_fp0")

(define_insn_reservation "ir_sb1_rsqrtsf_1pipe" 16
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "frsqrt")
	    (and (eq_attr "mode" "SF")
		 (eq_attr "sb1_fp_pipes" "one"))))
  "sb1_fp1")

;; ??? Can deliver at most 1 result per every 7 cycles because of issue
;; restrictions.

(define_insn_reservation "ir_sb1_rsqrtdf_2pipes" 28
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "frsqrt")
	    (and (eq_attr "mode" "DF")
		 (eq_attr "sb1_fp_pipes" "two"))))
  "sb1_fp1 | sb1_fp0")

(define_insn_reservation "ir_sb1_rsqrtdf_1pipe" 28
  (and (eq_attr "cpu" "sb1")
       (and (eq_attr "type" "frsqrt")
	    (and (eq_attr "mode" "DF")
		 (eq_attr "sb1_fp_pipes" "one"))))
  "sb1_fp1")