sh.h

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

/* Disable processor switches for which we have no suitable multilibs.  */
#ifndef SUPPORT_SH1
#define TARGET_SWITCH_SH1
#ifndef SUPPORT_SH2
#define TARGET_SWITCH_SH2
#ifndef SUPPORT_SH3
#define TARGET_SWITCH_SH3
#ifndef SUPPORT_SH4_NOFPU
#define TARGET_SWITCH_SH4_NOFPU
#endif
#ifndef SUPPORT_SH4A_NOFPU
#define TARGET_SWITCH_SH4A_NOFPU
#endif
#ifndef SUPPORT_SH4AL
#define TARGET_SWITCH_SH4AL
#endif
#ifndef SUPPORT_SH2A_NOFPU
#define TARGET_SWITCH_SH2A_NOFPU
#endif
#endif
#endif
#endif

#ifndef SUPPORT_SH2E
#define TARGET_SWITCH_SH2E
#ifndef SUPPORT_SH3E
#define TARGET_SWITCH_SH3E
#ifndef SUPPORT_SH4_SINGLE_ONLY
#define TARGET_SWITCH_SH4_SINGLE_ONLY
#endif
#ifndef SUPPORT_SH4A_SINGLE_ONLY
#define TARGET_SWITCH_SH4A_SINGLE_ONLY
#endif
#ifndef SUPPORT_SH2A_SINGLE_ONLY
#define TARGET_SWITCH_SH2A_SINGLE_ONLY
#endif
#endif
#endif

#ifndef SUPPORT_SH4
#define TARGET_SWITCH_SH4
#ifndef SUPPORT_SH4A
#define TARGET_SWITCH_SH4A
#endif
#endif

#ifndef SUPPORT_SH4_SINGLE
#define TARGET_SWITCH_SH4_SINGLE
#ifndef SUPPORT_SH4A_SINGLE
#define TARGET_SWITCH_SH4A_SINGLE
#endif
#endif

#ifndef SUPPORT_SH2A
#define TARGET_SWITCH_SH2A
#endif

#ifndef SUPPORT_SH2A_SINGLE
#define TARGET_SWITCH_SH2A_SINGLE
#endif

#ifndef SUPPORT_SH5_64MEDIA
#define TARGET_SWITCH_SH5_64MEDIA
#endif

#ifndef SUPPORT_SH5_64MEDIA_NOFPU
#define TARGET_SWITCH_SH5_64MEDIA_NOFPU
#endif

#if !defined(SUPPORT_SH5_32MEDIA) && !defined (SUPPORT_SH5_COMPACT)
#define TARGET_SWITCHES_SH5_32MEDIA
#endif

#if !defined(SUPPORT_SH5_32MEDIA_NOFPU) && !defined (SUPPORT_SH5_COMPACT_NOFPU)
#define TARGET_SWITCHES_SH5_32MEDIA_NOFPU
#endif

/* Reset all target-selection flags.  */
#define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
		      | HARD_SH2A_BIT | HARD_SH2A_DOUBLE_BIT \
		      | SH4A_BIT | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)

#ifndef TARGET_SWITCH_SH1
#define TARGET_SWITCH_SH1 \
  {"1",		TARGET_NONE, "" }, \
  {"1",		SELECT_SH1, "Generate SH1 code" },
#endif
#ifndef TARGET_SWITCH_SH2
#define TARGET_SWITCH_SH2 \
  {"2",		TARGET_NONE, "" }, \
  {"2",		SELECT_SH2, "Generate SH2 code" },
#endif
#ifndef TARGET_SWITCH_SH2E
#define TARGET_SWITCH_SH2E \
  {"2e",	TARGET_NONE, "" }, \
  {"2e",	SELECT_SH2E, "Generate SH2e code" },
#endif
#ifndef TARGET_SWITCH_SH2A
#define TARGET_SWITCH_SH2A \
  {"2a",	TARGET_NONE, "" }, \
  {"2a",	SELECT_SH2A, "Generate SH2a code" },
#endif
#ifndef TARGET_SWITCH_SH2A_SINGLE_ONLY
#define TARGET_SWITCH_SH2A_SINGLE_ONLY \
  {"2a-single-only", TARGET_NONE, "" },	\
  {"2a-single-only", SELECT_SH2A_SINGLE_ONLY, "Generate only single-precision SH2a code" },
#endif
#ifndef TARGET_SWITCH_SH2A_SINGLE
#define TARGET_SWITCH_SH2A_SINGLE \
  {"2a-single", TARGET_NONE, "" },	\
  {"2a-single", SELECT_SH2A_SINGLE, "Generate default single-precision SH2a code" },
#endif
#ifndef TARGET_SWITCH_SH2A_NOFPU
#define TARGET_SWITCH_SH2A_NOFPU \
  {"2a-nofpu",  TARGET_NONE, "" },	\
  {"2a-nofpu",  SELECT_SH2A_NOFPU, "Generate SH2a FPU-less code" },
#endif
#ifndef TARGET_SWITCH_SH3
#define TARGET_SWITCH_SH3 \
  {"3",		TARGET_NONE, "" }, \
  {"3",		SELECT_SH3, "Generate SH3 code" },
#endif
#ifndef TARGET_SWITCH_SH3E
#define TARGET_SWITCH_SH3E \
  {"3e",	TARGET_NONE, "" }, \
  {"3e",	SELECT_SH3E, "Generate SH3e code" },
#endif
#ifndef TARGET_SWITCH_SH4_SINGLE_ONLY
#define TARGET_SWITCH_SH4_SINGLE_ONLY \
  {"4-single-only",	TARGET_NONE, "" }, \
  {"4-single-only",	SELECT_SH4_SINGLE_ONLY, "Generate only single-precision SH4 code" },
#endif
#ifndef TARGET_SWITCH_SH4_SINGLE
#define TARGET_SWITCH_SH4_SINGLE \
  {"4-single",	TARGET_NONE, "" }, \
  {"4-single",	SELECT_SH4_SINGLE, "Generate default single-precision SH4 code" },
#endif
#ifndef TARGET_SWITCH_SH4_NOFPU
#define TARGET_SWITCH_SH4_NOFPU \
  {"4-nofpu",	TARGET_NONE, "" }, \
  {"4-nofpu",	SELECT_SH4_NOFPU, "Generate SH4 FPU-less code" },
#endif
#ifndef TARGET_SWITCH_SH4
#define TARGET_SWITCH_SH4 \
  {"4",		TARGET_NONE, "" }, \
  {"4",		SELECT_SH4, "Generate SH4 code" },
#endif
#ifndef TARGET_SWITCH_SH4A
#define TARGET_SWITCH_SH4A \
  {"4a",	TARGET_NONE, "" }, \
  {"4a",	SELECT_SH4A, "Generate SH4a code" },
#endif
#ifndef TARGET_SWITCH_SH4A_SINGLE_ONLY
#define TARGET_SWITCH_SH4A_SINGLE_ONLY \
  {"4a-single-only",	TARGET_NONE, "" },	\
  {"4a-single-only",	SELECT_SH4A_SINGLE_ONLY, "Generate only single-precision SH4a code" },
#endif
#ifndef TARGET_SWITCH_SH4A_SINGLE
#define TARGET_SWITCH_SH4A_SINGLE \
  {"4a-single",	TARGET_NONE, "" },\
  {"4a-single",	SELECT_SH4A_SINGLE, "Generate default single-precision SH4a code" },
#endif
#ifndef TARGET_SWITCH_SH4A_NOFPU
#define TARGET_SWITCH_SH4A_NOFPU \
  {"4a-nofpu",	TARGET_NONE, "" },\
  {"4a-nofpu",	SELECT_SH4A_NOFPU, "Generate SH4a FPU-less code" },
#endif
#ifndef TARGET_SWITCH_SH4AL
#define TARGET_SWITCH_SH4AL \
  {"4al",	TARGET_NONE, "" },\
  {"4al",	SELECT_SH4A_NOFPU, "Generate SH4al-dsp code" },
#endif
#ifndef TARGET_SWITCH_SH5_64MEDIA
#define TARGET_SWITCH_SH5_64MEDIA \
  {"5-64media",	TARGET_NONE, "" },		\
  {"5-64media", SELECT_SH5_64MEDIA, "Generate 64-bit SHmedia code" },
#endif
#ifndef TARGET_SWITCH_SH5_64MEDIA_NOFPU
#define TARGET_SWITCH_SH5_64MEDIA_NOFPU \
  {"5-64media-nofpu", TARGET_NONE, "" },	\
  {"5-64media-nofpu", SELECT_SH5_64MEDIA_NOFPU, "Generate 64-bit FPU-less SHmedia code" },
#endif
#ifndef TARGET_SWITCHES_SH5_32MEDIA
#define TARGET_SWITCHES_SH5_32MEDIA \
  {"5-32media",	TARGET_NONE, "" },		\
  {"5-32media", SELECT_SH5_32MEDIA, "Generate 32-bit SHmedia code" }, \
  {"5-compact",	TARGET_NONE, "" },		\
  {"5-compact",	SELECT_SH5_COMPACT, "Generate SHcompact code" },
#endif
#ifndef TARGET_SWITCHES_SH5_32MEDIA_NOFPU
#define TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
  {"5-32media-nofpu", TARGET_NONE, "" },	\
  {"5-32media-nofpu", SELECT_SH5_32MEDIA_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
  {"5-compact-nofpu", TARGET_NONE, "" },	\
  {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" },
#endif

#define TARGET_SWITCHES \
{ TARGET_SWITCH_SH1 \
  TARGET_SWITCH_SH2 \
  TARGET_SWITCH_SH2A_SINGLE_ONLY \
  TARGET_SWITCH_SH2A_SINGLE \
  TARGET_SWITCH_SH2A_NOFPU \
  TARGET_SWITCH_SH2A \
  TARGET_SWITCH_SH2E \
  TARGET_SWITCH_SH3 \
  TARGET_SWITCH_SH3E \
  TARGET_SWITCH_SH4_SINGLE_ONLY \
  TARGET_SWITCH_SH4_SINGLE \
  TARGET_SWITCH_SH4_NOFPU \
  TARGET_SWITCH_SH4 \
  TARGET_SWITCH_SH4A_SINGLE_ONLY \
  TARGET_SWITCH_SH4A_SINGLE \
  TARGET_SWITCH_SH4A_NOFPU \
  TARGET_SWITCH_SH4A \
  TARGET_SWITCH_SH4AL \
  TARGET_SWITCH_SH5_64MEDIA \
  TARGET_SWITCH_SH5_64MEDIA_NOFPU \
  TARGET_SWITCHES_SH5_32MEDIA \
  TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
  {"b",		-LITTLE_ENDIAN_BIT, "Generate code in big endian mode" },  	\
  {"bigtable", 	BIGTABLE_BIT, "Generate 32-bit offsets in switch tables" },		\
  {"dalign",  	DALIGN_BIT, "Aligns doubles at 64-bit boundaries" },		\
  {"fmovd",  	FMOVD_BIT, "" },		\
  {"hitachi",	HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" },		\
  {"renesas",	HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" },		\
  {"no-renesas",-HITACHI_BIT,"Follow the GCC calling conventions" },	\
  {"nomacsave", NOMACSAVE_BIT, "Mark MAC register as call-clobbered" },		\
  {"ieee",  	IEEE_BIT, "Increase the IEEE compliance for floating-point code" },			\
  {"isize", 	ISIZE_BIT, "" },		\
  {"l",		LITTLE_ENDIAN_BIT, "Generate code in little endian mode" },  	\
  {"no-ieee",  	-IEEE_BIT, "" },		\
  {"padstruct", PADSTRUCT_BIT, "" },    	\
  {"prefergot",	PREFERGOT_BIT, "Emit function-calls using global offset table when generating PIC" },		\
  {"relax",	RELAX_BIT, "Shorten address references during linking" },		\
  {"space", 	SPACE_BIT, "Deprecated. Use -Os instead" },		\
  {"usermode",	USERMODE_BIT, "Generate library function call to invalidate instruction cache entries after fixing trampoline" },		\
  SUBTARGET_SWITCHES                            \
  {"",   	TARGET_DEFAULT, "" } 		\
}

/* This are meant to be redefined in the host dependent files */
#define SUBTARGET_SWITCHES

/* This defaults us to big-endian.  */
#ifndef TARGET_ENDIAN_DEFAULT
#define TARGET_ENDIAN_DEFAULT 0
#endif

#define TARGET_DEFAULT  (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)

#ifndef SH_MULTILIB_CPU_DEFAULT
#define SH_MULTILIB_CPU_DEFAULT "m1"
#endif

#if TARGET_ENDIAN_DEFAULT
#define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
#else
#define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
#endif

#define CPP_SPEC " %(subtarget_cpp_spec) "

#ifndef SUBTARGET_CPP_SPEC
#define SUBTARGET_CPP_SPEC ""
#endif

#ifndef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS
#endif

#define EXTRA_SPECS						\
  { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },			\
  { "link_emul_prefix", LINK_EMUL_PREFIX },			\
  { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL },		\
  { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX },	\
  { "subtarget_link_spec", SUBTARGET_LINK_SPEC },		\
  { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC },	\
  { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC },	\
  { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC },	\
  SUBTARGET_EXTRA_SPECS

#if TARGET_CPU_DEFAULT & HARD_SH4_BIT
#define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
#else
#define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
#endif

#define SH_ASM_SPEC \
 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
%(subtarget_asm_isa_spec) %{m4al:-dsp}"

#define ASM_SPEC SH_ASM_SPEC

#ifndef SUBTARGET_ASM_ENDIAN_SPEC
#if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
#define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
#else
#define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
#endif
#endif

#define SUBTARGET_ASM_ISA_SPEC ""

#define LINK_EMUL_PREFIX "sh%{ml:l}"

#if TARGET_CPU_DEFAULT & SH5_BIT
#if TARGET_CPU_DEFAULT & SH_E_BIT
#define LINK_DEFAULT_CPU_EMUL "32"
#if TARGET_CPU_DEFAULT & SH1_BIT
#define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
#else
#define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
#endif /* SH1_BIT */
#else /* !SH_E_BIT */
#define LINK_DEFAULT_CPU_EMUL "64"
#define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
#endif /* SH_E_BIT */
#define ASM_ISA_DEFAULT_SPEC \
" %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
#else /* !SH5_BIT */
#define LINK_DEFAULT_CPU_EMUL ""
#define ASM_ISA_DEFAULT_SPEC ""
#endif /* SH5_BIT */

#define SUBTARGET_LINK_EMUL_SUFFIX ""
#define SUBTARGET_LINK_SPEC ""

/* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
   so that we can undo the damage without code replication.  */
#define LINK_SPEC SH_LINK_SPEC

#define SH_LINK_SPEC "\
-m %(link_emul_prefix)\
%{m5-compact*|m5-32media*:32}\
%{m5-64media*:64}\
%{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
%(subtarget_link_emul_suffix) \
%{mrelax:-relax} %(subtarget_link_spec)"

#define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE)				\
do {									\
  if (LEVEL)								\