lx_regs.h

潜入是烧写flash的程序

#define EXC_IBE		(6 << 2)	/* Bus error (Ifetch) */
#define EXC_DBE		(7 << 2)	/* Bus error (data load/store) */
#define EXC_SYS		(8 << 2)	/* System call */
#define EXC_BP		(9 << 2)	/* Break point */
#define EXC_RI		(10 << 2)	/* Reserved instruction */
#define EXC_CPU		(11 << 2)	/* Coprocessor unusable */
#define EXC_OVF		(12 << 2)	/* Arithmetic overflow */
#define EXC_TR          (13 << 2)       /* Trap instruction */

/* FPU stuff */
#define CSR_EMASK	(0x3f<<12)
#define CSR_TMASK	(0x1f<<7)
#define CSR_SMASK	(0x1f<<2)


/*** END OF STANDARD DEFINITIONS ***/


/*********************************************************************
 ** Lexra Specific Definitions
 **
 ** Included here are definitions of registers for:
 **  Coprocessor 3 (COPTC)
 **  BMC
 **  Vectored Interrupt (LX_INTVEC, LX_ESTATUS, LX_ECAUSE)
 **  Radiax extensions
 **  NetVortex extensions
 **  
 *********************************************************************
 */

/* CACHE CONTROL Symbols */

#define CCTL_DIvl	0x00000001	/* Invalidate Dcache */
#define CCTL_IIvl	0x00000002	/* Invalidate Icache/IRAM */
#define CCTL_ILk	0x00000004
#define CCTL_ILkM	0x00000008

/* Coprocessor 3 Control Registers */
#define C3_CON		$0

/* Coprocessor 3 General Registers */
#ifdef __ASSEMBLER__
#define C3_IWBASE	$0	/* IW Base Address [31:10] */
#define C3_IWTOP	$1	/* IW Top Address [15:4] */
#define C3_DWBASE	$4	/* DW Base Address [31:10] */
#define C3_DWTOP	$5	/* DW Top Address [15:4] */
#define C3_CNT0LO	$8	/* Counter 0 [31:0] */
#define C3_CNT0HI	$9	/* Counter 0 [47:32] */
#define C3_CNT1LO	$10	/* Counter 1 [31:0] */
#define C3_CNT1HI	$11	/* Counter 1 [47:32] */
#define C3_CNT2LO	$12	/* Counter 2 [31:0] */
#define C3_CNT2HI	$13	/* Counter 2 [47:32] */
#define C3_CNT3LO	$14	/* Counter 3 [31:0] */
#define C3_CNT3HI	$15	/* Counter 3 [47:32] */

#else

#define C3_IWBASE	0	/* IW Base Address [31:10] */
#define C3_IWTOP	1	/* IW Top Address [15:4] */
#define C3_DWBASE	4	/* DW Base Address [31:10] */
#define C3_DWTOP	5	/* DW Top Address [15:4] */
#define C3_CNT0LO	8	/* Counter 0 [31:0] */
#define C3_CNT0HI	9	/* Counter 0 [47:32] */
#define C3_CNT1LO	10	/* Counter 1 [31:0] */
#define C3_CNT1HI	11	/* Counter 1 [47:32] */
#define C3_CNT2LO	12	/* Counter 2 [31:0] */
#define C3_CNT2HI	13	/* Counter 2 [47:32] */
#define C3_CNT3LO	14	/* Counter 3 [31:0] */
#define C3_CNT3HI	15	/* Counter 3 [47:32] */

#endif

/*
** These are the registers used with the MTLXC0/MFLXC0 instructions.  Use
** of these registers is subject to COP0 useability exceptions.
** However, since they are not accessed by the MTC0/MFC0 instructions,
** they do not conflict with the COP0 list of register assignments.
*/

#ifdef __ASSEMBLER__
#define LX_ESTATUS	$0
#define LX_ECAUSE	$1
#define LX_INTVEC	$2
#define LX_CVSTAG	$3
#define LX_MOVECX	$4
#else
#define LX_ESTATUS	0
#define LX_ECAUSE	1
#define LX_INTVEC	2
#define LX_CVSTAG	3
#define LX_MOVECX	4
#endif

/*
** These are the registers used with the MTCXC/MFCXC instructions.  Use
** of these registers is subject to COP0 useability exceptions.
** However, since they are not accessed by the MTC0/MFC0 instructions,
** they do not conflict with the COP0 list of register assignments.
*/

#ifdef __ASSEMBLER__
#define CX_STATUS	$0
#define CX_PC    	$1
#else /* __ASSEMBLER__ */
#define CX_STATUS	0
#define CX_PC    	1
#endif /* __ASSEMBLER__ */

#ifndef  __ASSEMBLER__
extern unsigned int mflxc0(int reg);
extern void mtlxc0(int reg, unsigned int data);
extern unsigned int mfcxc(int reg);
extern void mtcxc(int reg, unsigned int data);
#endif /* __ASSEMBLER__ */




/* RADIAX
** These are the Radiax registers, used with the Radiax MAC, ZOV
** loops, post-modified pointers, etc.
*/


#ifdef __ASSEMBLER__

/* Accumulators */

#define m0l	$1		/* ma0l */
#define m0h	$2		/* ma0h */
#define m0	$3		/* ma0  */
#define m1l	$5		/* ma1l */
#define m1h	$6		/* ma1h */
#define m1	$7		/* ma1  */
#define m2l	$9		/* ma2l */
#define m2h	$10		/* ma2h */
#define m2	$11		/* ma2  */
#define m3l	$13		/* ma3l */
#define m3h	$14		/* ma3h */
#define m3	$15		/* ma3  */


/*
** These are the registers used with the MTRU/MFRU instructions.
*/

/* Circular buffer registers */

#define cbs0	$0		/* cs0 */
#define cbs1	$1		/* cs1 */
#define cbs2	$2		/* cs2 */
#define cbe0	$4		/* ce0 */
#define cbe1	$5		/* ce1 */
#define cbe2	$6		/* ce2 */

/* Zero Overhead Loop Control registers */

#define lps0	$16		/* ls0 */
#define lpe0	$17		/* le0 */
#define lpc0	$18		/* lc0 */

/* MAC Mode Register */

#define mmd	$24		/* md */

#else


/* Accumulators */

#define m0l	1		/* ma0l */
#define m0h	2		/* ma0h */
#define m0	3		/* ma0  */
#define m1l	5		/* ma1l */
#define m1h	6		/* ma1h */
#define m1	7		/* ma1  */
#define m2l	9		/* ma2l */
#define m2h	10		/* ma2h */
#define m2	11		/* ma2  */
#define m3l	13		/* ma3l */
#define m3h	14		/* ma3h */
#define m3	15		/* ma3  */


/*
** These are the registers used with the MTRU/MFRU instructions.
*/

/* Circular buffer registers */

#define cbs0	0		/* cs0 */
#define cbs1	1		/* cs1 */
#define cbs2	2		/* cs2 */
#define cbe0	4		/* ce0 */
#define cbe1	5		/* ce1 */
#define cbe2	6		/* ce2 */

/* Zero Overhead Loop Control registers */

#define lps0	16		/* ls0 */
#define lpe0	17		/* le0 */
#define lpc0	18		/* lc0 */

/* MAC Mode Register */

#define mmd	24		/* md */

#endif






/* Processor IDs */
/* Are these obsolete? */

#define PRID_LX4080	0xC0	/* Lexra LX-4080 CPU Core	ISA I	*/
#define PRID_LX4080P0	0x0201	/* Lexra LX-4080-P0 CPU Core	ISA I	*/
#define PRID_LX4180	0xC1	/* Lexra LX-4180 CPU Core	ISA I	*/
#define PRID_LX4280	0xC2	/* Lexra LX-4280 CPU Core	ISA I	*/
#define PRID_LX4089	0xC3	/* Lexra LX-4089 CPU Core	ISA I	*/
#define PRID_LX4189	0xC4	/* Lexra LX-4189 CPU Core	ISA I	*/
#define PRID_LX5180	0xC5	/* Lexra LX-5180 CPU Core	ISA I	*/
#define PRID_LX5280	0xC6	/* Lexra LX-5280 CPU Core	ISA I	*/
#define PRID_LX8000	0xC7	/* Lexra LX-8000 CPU Core	ISA I	*/
#define PRID_LX4087	0xC8	/* Lexra LX-4087 CPU Core	ISA I	*/
#define PRID_LX4187	0xC9	/* Lexra LX-4187 CPU Core	ISA I	*/
#define PRID_LX4287	0xCA	/* Lexra LX-4287 CPU Core	ISA I	*/
#define PRID_LX5187	0xCB	/* Lexra LX-5187 CPU Core	ISA I	*/
#define PRID_LX5287	0xCC	/* Lexra LX-5287 CPU Core	ISA I	*/





/****************************************/

#ifdef __ASSEMBLER__

/* BMC general registers */

#define BMC_CBUSADR		$16
#define BMC_DMEMADR		$17
#define BMC_XFERLEN		$18
#define BMC_PARAM		$19
#define BMC_CMD         	$20

/* BMC control registers */

#define BMC_DONEVEC		$17
#define BMC_INTLOW		$18
#define BMC_INTENVEC		$19

#else

/* BMC general registers */

#define BMC_CBUSADR		16
#define BMC_DMEMADR		17
#define BMC_XFERLEN		18
#define BMC_PARAM		19
#define BMC_CMD         	20

/* BMC control registers */

#define BMC_DONEVEC		17
#define BMC_INTLOW		18
#define BMC_INTENVEC		19

#endif

/* BMC_PARAM bit fields */

#define BMC_PARAMTYPEMASK   	(0x0f<<20)
#define BMC_PARAMTYPEREAD	(0x01<<20)
#define BMC_PARAMTYPEWRITE	(0x02<<20)
#define BMC_PARAMINT		(0x01<<17)
#define BMC_PARAMINC		(0x01<< 3)
#define BMC_PARAMLINE		(0x01<< 2)
#define BMC_PARAMTWIN		(0x01<< 1)
#define BMC_PARAMWORD		(0x01<< 0)

/* BMC_CMD bit fields */

#define BMC_CMDBUSY		(0x01<<31)
#define BMC_CMDCMDMASK		(0x07<< 0)
#define BMC_CMDCMDCLEAR		(0x00<< 0)
#define BMC_CMDCMDSTART		(0x01<< 0)
#define BMC_CMDCMDSTOP		(0x02<< 0)

/****************************************/

#endif