interfacing the enhanced parallel port.htm

并口的接口规范

            <TD>Ground</TD></TR></TBODY></TABLE><FONT size=-1>Table 1. Pin 
        Assignments For Enhanced Parallel Port Connector.</FONT></CENTER>
        <P>Paper Out, Select and Error are not defined in the EPP handshake. 
        These lines can be utilised in any way by the user. The status of these 
        lines can be determined at anytime by viewing the SPP Status Register. 
        Unfortunately there are no spare output's. This can become a hassle 
        regularly. </P></UL><A name=3><I><FONT size=+2>The EPP 
      Handshake</FONT></I></A> 
      <HR>

      <UL>
        <P>In order to perform a valid exchange of data using EPP we must follow 
        the EPP handshake. As the hardware does all the work, this handshake 
        only requires to be used for your hardware and not for software as the 
        case with SPP. To initiate an EPP cycle your software needs to perform 
        only one I/O operation to the relevant EPP Register. Details on this, 
        latter. </P><A name=4><I><FONT size=+2>EPP Data Write 
        Cycle</FONT></I></A> 
        <HR>
        <BR>
        <CENTER>
        <TABLE boarder="0">
          <TBODY>
          <TR>
            <TD><IMG alt="Enhanced Parallel Port Data Write Cycle" 
              src="Interfacing the Enhanced Parallel Port.files/eppdatwr.gif" 
              border=0> <BR>
              <CENTER><FONT size=-1>Figure 1. Enhanced Parallel Port Data Write 
              Cycle.</FONT></CENTER></TD>
            <TD><B>1. Program writes to EPP Data Register. (Base + 
              4)<BR></B>2. nWrite is placed low. (Low indicates write 
              operation)<BR><B>3. Data is placed on Data Lines 0-7.<BR></B>4. 
              nData Strobe is asserted if Wait is Low (O.K. to start 
              cycle)<BR><B>5. Host waits for Acknowledgment by nWait going high 
              (O.K. to end cycle)<BR></B>6. nData Strobe is 
              de-asserted.<BR><B>7. EPP Data Write Cycle 
          Ends.<BR></B></TD></TR></TBODY></TABLE></CENTER><BR><A name=5><I><FONT 
        size=+2>EPP Address Write Cycle</FONT></I></A> 
        <HR>
        <BR>
        <CENTER>
        <TABLE boarder="0">
          <TBODY>
          <TR>
            <TD><IMG alt="Enhanced Parallel Port Address Write Cycle" 
              src="Interfacing the Enhanced Parallel Port.files/eppadrwr.gif" 
              border=0> <BR>
              <CENTER><FONT size=-1>Figure 2. Enhanced Parallel Port Address 
              Write Cycle.</FONT></CENTER></TD>
            <TD><B>1. Program writes address to EPP's Address Register (Base + 
              3)<BR></B>2. Write is placed low. (Low indicates write 
              operation)<BR><B>3. Address is placed on Data Lines 0-7.<BR></B>4. 
              Address Strobe is asserted if Wait is Low (O.K. to start 
              cycle)<BR><B>5. Host waits for Acknowledgment by wait going high 
              (O.K. to end cycle)<BR></B>6. nAddress Strobe is De-asserted. 
              <BR><B>7. EPP Address Write Cycle 
        Ends.<BR></B></TD></TR></TBODY></TABLE></CENTER><BR><A name=6><I><FONT 
        size=+2>EPP Data Read Cycle</FONT></I></A> 
        <HR>
        <BR>
        <CENTER>
        <TABLE boarder="0">
          <TBODY>
          <TR>
            <TD><IMG alt="Enhanced Parallel Port Data Read Cycle" 
              src="Interfacing the Enhanced Parallel Port.files/eppdatrd.gif" 
              border=0> <BR>
              <CENTER><FONT size=-1>Figure 3. Enhanced Parallel Port Data Read 
              Cycle.</FONT></CENTER></TD>
            <TD><B>1. Program reads EPP Data Register. (Base + 4)<BR></B>2. 
              nData Strobe is asserted if Wait is Low (O.K. to start 
              cycle)<BR><B>3. Host waits for Acknowledgment by nWait going 
              high<BR></B>4. Data is read from Parallel Port Pins.<BR><B>5. 
              nData Strobe is de-asserted.<BR></B>6. EPP Data Read Cycle 
              Ends.<BR></B></TD></TR></TBODY></TABLE></CENTER><BR><A name=7><I><FONT 
        size=+2>EPP Address Read Cycle</FONT></I></A> 
        <HR>
        <BR>
        <CENTER>
        <TABLE boarder="0">
          <TBODY>
          <TR>
            <TD><IMG alt="Enhanced Parallel Port Address Read Cycle" 
              src="Interfacing the Enhanced Parallel Port.files/eppadrrd.gif" 
              border=0> <BR>
              <CENTER><FONT size=-1>Figure 4. Enhanced Parallel Port Address 
              Read Cycle.</FONT></CENTER></TD>
            <TD><B>1. Program reads EPP Address Register. (Base + 3)<BR></B>2. 
              nAddr Strobe is asserted if Wait is Low (O.K. to start 
              cycle)<BR><B>3. Host waits for Acknowledgment by nWait going 
              high<BR></B>4. Data is read from Parallel Port Pins.<BR><B>5. 
              nAddr Strobe is de-asserted.<BR></B>6. EPP Address Read Cycle 
              Ends.<BR></B></TD></TR></TBODY></TABLE></CENTER><BR>
        <TABLE>
          <TBODY>
          <TR>
            <TD vAlign=top><I>Note </I></TD>
            <TD>If implementing EPP 1.7 Handshake (Pre IEEE 1284) the Data and 
              Address Strobes can be asserted to start a cycle regardless of the 
              wait state. EPP 1.9 will only start a cycle once wait is low. Both 
              EPP 1.7 and EPP 1.9 require the wait to be high to finish a 
              cycle.</I> </TD></TR></TBODY></TABLE></UL><A name=8><I><FONT size=+2>The 
      EPP's Software Registers.</FONT></I></A> 
      <HR>

      <UL>
        <P>The EPP Port also has a new set of registers. However 3 of them have 
        been inherited from the Standard Parallel Port. Below is a table showing 
        the new and existing registers. </P><BR>
        <CENTER>
        <TABLE width="70%" border=1>
          <TBODY>
          <TR>
            <TD>
              <CENTER><B>Address</B></CENTER></TD>
            <TD>
              <CENTER><B>Port Name</B></CENTER></TD>
            <TD>
              <CENTER><B>Read/Write</B></CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>Base + 0</CENTER></TD>
            <TD>
              <CENTER>Data Port (SPP)</CENTER></TD>
            <TD>
              <CENTER>Write</CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>Base + 1</CENTER></TD>
            <TD>
              <CENTER>Status Port (SPP)</CENTER></TD>
            <TD>
              <CENTER>Read</CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>Base + 2</CENTER></TD>
            <TD>
              <CENTER>Control Port (SPP)</CENTER></TD>
            <TD>
              <CENTER>Write</CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>Base + 3</CENTER></TD>
            <TD>
              <CENTER>Address Port (EPP)</CENTER></TD>
            <TD>
              <CENTER>Read/Write</CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>Base + 4</CENTER></TD>
            <TD>
              <CENTER>Data Port (EPP)</CENTER></TD>
            <TD>
              <CENTER>Read/Write</CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>Base + 5</CENTER></TD>
            <TD>
              <CENTER>Undefined (16/32bit Transfers)</CENTER></TD>
            <TD>
              <CENTER>-</CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>Base + 6</CENTER></TD>
            <TD>
              <CENTER>Undefined (32bit Transfers)</CENTER></TD>
            <TD>
              <CENTER>-</CENTER></TD></TR>
          <TR>
            <TD>
              <CENTER>Base + 7</CENTER></TD>
            <TD>
              <CENTER>Undefined (32bit Transfers)</CENTER></TD>
            <TD>
              <CENTER>-</CENTER></TD></TR></TBODY></TABLE><FONT size=-1>Table 2 EPP 
        Registers</FONT></CENTER>
        <P>As you can see, the first 3 addresses are exactly the same than the 
        Standard Parallel Port Register and behave in exactly the same way. 
        Therefore if you used a Enhanced Parallel Port, you can output data to 
        Base + 0 in exactly the same fashion than you would if it was a Standard 
        Parallel Port (SPP). If you were to connect a printer, and use 
        compatibility mode then you would have to check to see if the port is 
        busy and then assert &amp; de-assert the strobe using the Control and 
        Status Port, then wait for the Ack. </P>
        <P>If you wish to communicate with a EPP compatible device then all you 
        have to do, is place any data you wish to send in the EPP Data Register 
        at Base + 4 and the card will generate all the necessary handshaking 
        required. Likewise if you wish to send an address to your device, then 
        you use the EPP Address Register at offset +3. </P>
        <P>Both the EPP Address Register and the EPP Data Register are read / 
        write, thus to read data from your device, you can use the same 
        registers. However the EPP Printer Card has to initiate a read Cycle as 
        both the nData Strobe and nAddress Strobe are outputs. Your device can 
        signal a read request via the use of the interrupt and have your ISR 
        perform the Read Operation. </P>
        <P>The Status Port has one little modification. Bit 0, which was 
        reserved in the SPP register set, now becomes the EPP Time-out Bit. This 
        bit will be set when an EPP time-out occurs. This happens when the nWait 
        line is not deasserted within approximately 10uS (depending upon the 
        port) of the IOW or IOR line being asserted. The IOW and IOR are the I/O 
        Read and Write lines present on the ISA Bus. </P>
        <P>The EPP mode is very depended of the ISA bus timing. When a read 
        cycle is performed, the port must undertake the appropriate Read/Write 
        handshake and return the data in that ISA cycle. Of course this doesn't 
        occur within one ISA cycle, thus the port uses the IOCHRDY (I/O Channel 
        Ready) on the ISA bus to introduce wait states, until the cycle 
        completes. Now imagine if a EPP Read or Write is started with no 
        peripheral connected? The port never gets an acknowledgment (nWait), 
        thus keeps sending requests for wait states, and your computer locks up. 
        Therefore the EPP implements a type of watchdog, which times out after 
        approximately 10uS. </P>
        <P>The three registers, Base + 5, Base + 6 and Base + 7 can be used for 
        16 and 32 bit read/write operations if your port supports it. This can 
        further reduce your I/O operations. The Parallel Port can only transport 
        8 bits at a time, thus any 32 or 16 bit word written to the Parallel 
        Port will be split into byte size blocks and sent via the Parallel 
        Port's 8 data lines. </P></UL><A name=9><I><FONT size=+2>EPP Programming 
      Considerations.</FONT></I></A> 
      <HR>

      <UL><I>
        <P>EPP only has two main registers and a Time-out Status Flag, What 
        could there possibly be to set up? </P></I>
        <P>Before you can start any EPP cycles by reading and writing to the EPP 
        Data and Address Ports, the port must be configured correctly. In the 
        idle state, an EPP port should have it's nAddress Strobe, nData Strobe, 
        nWrite and nReset lines inactive, high. Some ports require you to set 
        this up before starting any EPP Cycle. Therefore our first task is to 
        manually initialise these lines using the SPP Registers. Writing 
        XXXX0100 to the control port will do this. </P>
        <P>On some cards, if the Parallel Port is placed in reverse mode, a EPP 
        Write cycle cannot be performed. Therefore it is also wise to place the 
        Parallel Port in forward mode before using EPP. Clearing Bit 5 of the 
        Control Register should result in an more enjoyable programming session, 
        without tearing your hair out. </P>
        <P>The EPP Timeout bit we have already discussed. When this bit is set, 
        the EPP port may not function correctly. A common scenario is always 
        reading 0xFF from either the Address or Data Cycles. This bit should be 
        cleared for reliable operation, and constantly checked. 
    </P></UL><BR><BR></TD></TR></TBODY></TABLE><FONT size=2>Copyright 1997-2005 <A 
href="http://www.beyondlogic.org/about.htm">Craig Peacock</A> - 15th June 
2005.</FONT> <BR><BR></CENTER></BODY></HTML>