interfacing the standard parallel port.htm

并口的接口规范

 printf("IRQ %d : INTNO %02X : PIC Addr 0x%X : Mask 0x%02X\n",IRQ,intno,picaddr,picmask);
 interflag = 0; /* Reset Interrupt Flag */
 delay(10);
 outportb(DATA,0x00); /* High to Low Transition */
 delay(10);           /* Wait */
 if (interflag == 1) printf("Interrupts Occur on High to Low Transition of ACK.\n");
 else
   {
    outportb(DATA,0xFF); /* Low to High Transition */
    delay(10);           /* wait */
    if (interflag == 1) printf("Interrupts Occur on Low to High Transition of ACK.\n");
    else printf("No Interrupt Activity Occurred. \nCheck IRQ Number, Port Address and Wiring.");
    }

 outportb(CONTROL, inportb(CONTROL) & 0xEF); /* Disable Parallel Port IRQ's */
 outportb(picaddr+1,inportb(picaddr+1) | picmask); /* Mask Pic */
 setvect(intno, oldhandler); /* Restore old Interrupt Vector Before Exit */
}
</PRE></UL><PRE></PRE><FONT face=ARIAL>
        <P>At compile time, the above source may generate a few warnings, 
        condition always true, condition always false, unreachable code etc. 
        These are perfectly O.K. They are generated as some of the condition 
        structures test which IRQ you are using, and as the IRQ is defined as a 
        constant some outcomes will never change. While they would of been 
        better implemented as a preprocessor directive, I've done this so you 
        can cut and paste the source code in your own programs which may use 
        command line arguments, user input etc instead of a defined IRQ. </P>
        <P>To understand how this example works, the reader must have an assumed 
        knowledge and understanding of Interrupts and Interrupt Service Routines 
        (ISR). If not, See <A 
        href="http://www.beyondlogic.org/interrupts/interupt.htm">Interfacing 
        the PC : Using Interrupts</A> for a quick introduction. </P>
        <P>The first part of the mainline routine calculates the Interrupt 
        Vector, PIC Addr &amp; Mask in order to use the Parallel Port's 
        Interrupt Facility. After the Interrupt Service Routine (ISR) has been 
        set up and the Programmable Interrupt Controller (PIC) set, we must 
        enable the interrupt on the Parallel Port. This is done by setting bit 4 
        of the Parallel Port's Control Register using <PRE>outportb(CONTROL,inportb(CONTROL) | 0x10);</PRE>
        <P></P>
        <P>Before enabling the interrupts, we wrote 0xFF to the Parallel Port to 
        enable the 8 data lines into a known state. At this point of the 
        program, all the data lines should be high. The interrupt service 
        routine simply sets a flag (interflag), thus we can determine when an 
        IRQ occurs. We are now in a position to write 0x00 to the data port, 
        which causes a high to low transition on the Parallel Port's Acknowledge 
        line as it's connected to one of the data lines. </P>
        <P>If the interrupt occurs on the high to low transition, the interrupt 
        flag (interflag) should be set. We now test this, and if this is so the 
        program informs the user. However if it is not set, then an interrupt 
        has not yet occurred. We now write 0xFF to the data port, which will 
        cause a low to high transition on the nAck line and check the interrupt 
        flag again. If set, then the interrupt occurs on the low to high 
        transition. </P>
        <P>However if the interrupt flag is still reset, then this would suggest 
        that the interrupts are not working. Make sure your IRQ and Base Address 
        is correct and also check the wiring of the plug. </P></UL><A 
      name=10><I><FONT size=+2>Parallel Port Modes in BIOS</FONT></I>
      <HR>
      </A> 
      <UL>
        <P>Today, most Parallel Ports are mulimode ports. They are normally 
        software configurable to one of many modes from BIOS. The typical modes 
        are, </P>
        <UL>Printer Mode (Sometimes called Default or Normal 
          Modes)<BR>Standard &amp; Bi-directional (SPP) Mode<BR>EPP1.7 and SPP 
          Mode<BR>EPP1.9 and SPP Mode<BR>ECP Mode<BR>ECP and EPP1.7 Mode<BR>ECP 
          and EPP1.9 Mode<BR></UL>
        <P><I>Printer Mode</I> is the most basic mode. It is a Standard Parallel 
        Port in forward mode only. It has no bi-directional feature, thus Bit 5 
        of the Control Port will not respond. <I>Standard &amp; Bi-directional 
        (SPP) Mode</I> is the bi-directional mode. Using this mode, bit 5 of the 
        Control Port will reverse the direction of the port, so you can read 
        back a value on the data lines. </P>
        <P><I>EPP1.7 and SPP Mode</I> is a combination of EPP 1.7 (Enhanced 
        Parallel Port) and SPP Modes. In this mode of operation you will have 
        access to the SPP registers (Data, Status and Control) and access to the 
        EPP Registers. In this mode you should be able to reverse the direction 
        of the port using bit 5 of the control register. EPP 1.7 is the earlier 
        version of EPP. This version, version 1.7, may not have the time-out 
        bit. See <A href="http://www.beyondlogic.org/epp/epp.htm">Interfacing 
        the Enhanced Parallel Port</A> for more information. </P>
        <P><I>EPP1.9 and SPP Mode</I> is just like the previous mode, only it 
        uses EPP Version 1.9 this time. As in the other mode, you will have 
        access to the SPP registers, including Bit 5 of the control port. 
        However this differs from EPP1.7 and SPP Mode as you should have access 
        to the EPP Timeout bit. </P>
        <P><I>ECP Mode</I> will give you an Extended Capabilities Port. The mode 
        of this port can then be set using the ECP's Extended Control Register 
        (ECR). However in this mode from BIOS the EPP Mode (100) will not be 
        available. We will further discuss the ECP's Extended Control Register 
        in this document, but if you want further information on the ECP port, 
        consult <A href="http://www.beyondlogic.org/ecp/ecp.htm">Interfacing the 
        Extended Capabilities Port.</A> </P>
        <P><I>ECP and EPP1.7 Mode</I> and <I>ECP and EPP1.9 Mode</I> will give 
        you an Extended Capabilities Port, just like the previous mode. However 
        the EPP Mode in the ECP's ECR will now be available. Should you be in 
        <I>ECP and EPP1.7 Mode</I> you will get an EPP1.7 Port, or if you are in 
        <I>ECP and EPP1.9 Mode</I>, an EPP1.9 Port will be at your disposal. 
</P>
        <P>The above modes are configurable via BIOS. You can reconfigure them 
        by using your own software, but this is <B>not recommended</B>. These 
        software registers, typically found at 0x2FA, 0x3F0, 0x3F1 etc are only 
        intended to be accessed by BIOS. There is no set standard for these 
        configuration registers, thus if you were to use these registers, your 
        software would not be very portable. With today's multitasking operating 
        systems, its also not a good idea to change them when it suits you. </P>
        <P>A better option is to select <I>ECP and EPP1.7 Mode</I> or <I>ECP and 
        EPP1.9 Mode</I> from BIOS and then use the ECP's Extended Control 
        Register to select your Parallel Port's Mode. The EPP1.7 mode had a few 
        problems in regards to the Data and Address Strobes being asserted to 
        start a cycle regardless of the wait state, thus this mode if not 
        typically used now. Best set your Parallel Port to <I>ECP and EPP1.9 
        Mode.</I> </P></UL><A name=11><I><FONT size=+2>Parallel Port Modes and the 
      ECP's Extended Control Register</FONT></I>
      <HR>
      </A> 
      <UL>
        <P>As we have just discussed, it is better to set the Parallel Port to 
        <I>ECP and EPP1.9 Mode</I> and use the ECP's Extended Control Register 
        to select different modes of operation. The ECP Registers are 
        standardized under Microsoft's <B>Extended Capabilities Port Protocol 
        and ISA Interface Standard</B>, thus we don't have that problem of every 
        vendor having their own register set. </P>
        <P>When set to ECP Mode, a new set of registers become available at Base 
        + 0x400h. A discussion of these registers are available in <A 
        href="http://www.beyondlogic.org/ecp/ecp.htm">Interfacing the Extended 
        Capabilities Port</A>. Here we are only interested in the Extended 
        Control Register (ECR) which is mapped at Base + 0x402h. It should be 
        stated that the ECP's registers are not available for port's with a base 
        address of 0x3BCh. </P>
        <P>
        <CENTER>
        <TABLE width="65%" border=1>
          <TBODY>
          <TR>
            <TD width="10%">
              <CENTER><B>Bit</B></CENTER></TD>
            <TD colSpan=2>
              <CENTER><B>Function</B></CENTER></TD></TR>
          <TR>
            <TD vAlign=top rowSpan=9>
              <CENTER>7:5</CENTER></TD>
            <TD colSpan=2><I>Selects Current Mode of Operation</I></TD></TR>
          <TR>
            <TD width="10%">
              <CENTER>000</CENTER></TD>
            <TD>Standard Mode</TD></TR>
          <TR>
            <TD>
              <CENTER>001</CENTER></TD>
            <TD>Byte Mode</TD></TR>
          <TR>
            <TD>
              <CENTER>010</CENTER></TD>
            <TD>Parallel Port FIFO Mode</TD></TR>
          <TR>
            <TD>
              <CENTER>011</CENTER></TD>
            <TD>ECP FIFO Mode</TD></TR>
          <TR>
            <TD>
              <CENTER>100</CENTER></TD>
            <TD>EPP Mode</TD></TR>
          <TR>
            <TD>
              <CENTER>101</CENTER></TD>
            <TD>Reserved</TD></TR>
          <TR>
            <TD>
              <CENTER>110</CENTER></TD>
            <TD>FIFO Test Mode</TD></TR>
          <TR>
            <TD>
              <CENTER>111</CENTER></TD>
            <TD>Configuration Mode</TD></TR>
          <TR>
            <TD>
              <CENTER>4</CENTER></TD>
            <TD colSpan=2>ECP Interrupt Bit</TD></TR>
          <TR>
            <TD>
              <CENTER>3</CENTER></TD>
            <TD colSpan=2>DMA Enable Bit</TD></TR>
          <TR>
            <TD>
              <CENTER>2</CENTER></TD>
            <TD colSpan=2>ECP Service Bit</TD></TR>
          <TR>
            <TD>
              <CENTER>1</CENTER></TD>
            <TD colSpan=2>FIFO Full</TD></TR>
          <TR>
            <TD>
              <CENTER>0</CENTER></TD>
            <TD colSpan=2>FIFO Empty</TD></TR></TBODY></TABLE><FONT size=-1>Table 7 
        - Extended Control Register (ECR)</FONT></CENTER>
        <P></P>
        <P>The table above is of the Extended Control Register. We are only 
        interested in the three MSB of the Extended Control Register which 
        selects the mode of operation. There are 7 possible modes of operation, 
        but not all ports will support all modes. The EPP mode is one such 
        example, not being available on some ports. </P>
        <P>
        <CENTER>
        <TABLE width="90%">
          <TBODY>
          <TR>
            <TD width="25%" colSpan=2>
              <CENTER>
              <HR>
              <B>Modes of Operation</B>
              <HR>
              </CENTER></TD></TR>
          <TR>
            <TD vAlign=top>Standard Mode</TD>
            <TD>Selecting this mode will cause the ECP port to behave as a 
              Standard Parallel Port, without bi-directional functionality. 
          </TD></TR>
          <TR>
            <TD vAlign=top>Byte Mode / PS/2 Mode</TD>
            <TD>Behaves as a SPP in bi-directional mode. Bit 5 will place the 
              port in reverse mode. </TD></TR>
          <TR>
            <TD vAlign=top>Parallel Port FIFO Mode</TD>
            <TD>In this mode, any data written to the Data FIFO will be sent 
              to the peripheral using the SPP Handshake. The hardware will 
              generate the handshaking required. Useful with non-ECP devices 
              such as Printers. You can have some of the features of ECP like 
              FIFO buffers and hardware generation of handshaking but爓ith the 
              existing SPP爃andshake instead of the ECP燞andshake.</TD></TR>
          <TR>
            <TD vAlign=top>ECP FIFO Mode</TD>
            <TD>Standard mode for ECP use. This mode uses the ECP Handshake 
              described in Interfacing the Extended Capabilities Port. - <I>When 
              in ECP Mode though BIOS, and the ECR register is set to ECP FIFO 
              Mode (011), the SPP registers may disappear.</I></TD></TR>
          <TR>
            <TD vAlign=top>EPP Mode<I>/Reserved</I></TD>
            <TD>This will enable EPP Mode, if available. Under BIOS, if ECP 
              mode is set then it's more than likely, this mode is not an 
              option. However if BIOS is set to ECP and EPP1.x Mode, then EPP 
              1.x will be enabled. - <I>Under Microsoft's <B>Extended 
              Capabilities Port Protocol and ISA Interface Standard</B> this 
              mode is Vendor Specified.</I></TD></TR>
          <TR>
            <TD vAlign=top>Reserved</TD>
            <TD>Currently Reserved. - <I>Under Microsoft's <B>Extended 
              Capabilities Port Protocol and ISA Interface Standard</B> this 
              mode is Vendor Specified.</I></TD></TR>
          <TR>
            <TD vAlign=top>FIFO Test Mode</TD>
            <TD>While in this mode, any data written to the Test FIFO Register 
              will be placed into the FIFO and any data read from the Test FIFO 
              register will be read from the FIFO燽uffer. The FIFO Full/Empty 
              Status Bits will reflect their true value, thus FIFO depth, among 
              other things can be determined in this mode. </TD></TR>
          <TR>
            <TD vAlign=top>Configuration Mode</TD>
            <TD>In this mode, the two configuration registers, cnfgA &amp; 
              cnfgB become available at their designated register 
          addresses.</TD></TR>
          <TR>
            <TD colSpan=2>
              <HR>
            </TD></TR></TBODY></TABLE></CENTER>
        <P></P>
        <P>If you are in ECP Mode under BIOS, or if your card is jumpered to use 
        ECP then it is a good idea to initialize the mode of your ECP port to a 
        pre-defined state before use. If you are using SPP, then set the port to 
        Standard Mode as the first thing you do. Don't assume that the port wil