epp mode.htm

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      peripheral device. This "speed adaptive" property is transparent to both 
      the host and peripheral. All 1284 transfer modes are implemented with 
      interlocking handshakes. </FONT><FONT face="Arial, Helvetica, sans-serif" 
      color=#000000></FONT></P>
      <P align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=1>Interlocking refers to the criteria that each control signal 
      transition is acknowledged by the opposite side of the interface. In the 
      above diagram, nDataStrobe can be asserted because nWAIT is low, nWAIT 
      deasserts in response to nDataStrobe be asserted, nDataStrobe deasserts in 
      response to nWAIT being deasserted, and finally nWAIT asserts in response 
      to nDataStrobe being deasserted. In this way the peripheral can control 
      the setup time required for its operation. This is done in the following 
      manner: the setup time is the time from the assertion of nDataStrobe to 
      the deassertion of nWAIT, the peripherals controls this time. Interlocking 
      also has the advantage of making the transfer cycle independent of the 
      cable length. The Nibble, Byte, EPP and ECP modes all have interlocked 
      protocols. </FONT></P>
      <P align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=1>As previously mentioned, the pre-1284 EPP devices deviated from the 
      1284 protocol. At the start of the cycle, the nDataStrobe or nAddrStrobe 
      would assert regardless of the state of the nWAIT signal. This means that 
      the peripheral could not hold off the start of a cycle by having nWAIT 
      deasserted. This is sometimes referred to as EPP 1.7, in reference to a 
      Xircom proposal version 1.7. This is the version that Intel implemented in 
      the original 82360 I/O controller. A 1284 EPP compatible peripheral will 
      work properly with an EPP 1.7 version host adapter, but an EPP 1.7 
      peripheral may not operate properly with a 1284 compliant host. Figure 2 
      is an example of an Address_Read cycle. </FONT></P>
      <P align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000><IMG 
      height=176 src="EPP Mode.files/eppfig2.gif" width=436><BR></FONT></P>
      <CENTER><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=1>Figure 2 -- EPP Address_Read Cycle</FONT> </CENTER>
      <H3 align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=2>EPP Register Interface</FONT></H3>
      <P align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=1>The simplest software view of EPP is that of an extension to the 
      register definitions for the standard parallel port. As shown earlier, the 
      SPP consists of three registers, offset from the port's base address: Data 
      port, Status port, and Control port. The most common EPP implementations 
      expand this to use ports not defined by the SPP. See table 2. </FONT></P>
      <H4 align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=2>Table 2 EPP Register Definitions</FONT></H4>
      <DIV align=left>
      <TABLE width=520 border=1>
        <TBODY>
        <TR>
          <TH><FONT face="Arial, Helvetica, sans-serif" size=2>Port 
          Name</FONT></TH>
          <TH><FONT face="Arial, Helvetica, sans-serif" 
size=2>Offset</FONT></TH>
          <TH><FONT face="Arial, Helvetica, sans-serif" size=2>Mode</FONT></TH>
          <TH><FONT face="Arial, Helvetica, sans-serif" 
            size=2>Read/Write</FONT></TH>
          <TH><FONT face="Arial, Helvetica, sans-serif" 
            size=2>Description</FONT></TH></TR>
        <TR>
          <TD><FONT face="Arial, Helvetica, sans-serif" size=1>SPP Data 
            Port</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>+0</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>SPP/EPP</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>W</FONT></TD>
          <TD><FONT face="Arial, Helvetica, sans-serif" size=1>Standard SPP 
            data port. No autostrobing.</FONT></TD></TR>
        <TR>
          <TD><FONT face="Arial, Helvetica, sans-serif" size=1>SPP Status 
            Port</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>+1</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>SPP/EPP</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>R</FONT></TD>
          <TD><FONT face="Arial, Helvetica, sans-serif" size=1>Reads the input 
            status lines on the interface.</FONT></TD></TR>
        <TR>
          <TD><FONT face="Arial, Helvetica, sans-serif" size=1>SPP Control 
            Port</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>+2</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>SPP/EPP</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>W</FONT></TD>
          <TD><FONT face="Arial, Helvetica, sans-serif" size=1>Sets the state 
            of the output control lines.</FONT></TD></TR>
        <TR>
          <TD><FONT face="Arial, Helvetica, sans-serif" size=1>EPP Address 
            Port</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>+3</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>EPP</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>R/W</FONT></TD>
          <TD><FONT face="Arial, Helvetica, sans-serif" size=1>Generates an 
            interlocked address read or write cycle.</FONT></TD></TR>
        <TR>
          <TD><FONT face="Arial, Helvetica, sans-serif" size=1>EPP Data 
            Port</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>+4</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>EPP</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>R/W</FONT></TD>
          <TD><FONT face="Arial, Helvetica, sans-serif" size=1>Generates an 
            interlocked data read or write cycle.</FONT></TD></TR>
        <TR>
          <TD><FONT face="Arial, Helvetica, sans-serif" size=1>Not 
            Defined</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" size=1>+5 
            to +7</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>EPP</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            size=1>N/A</FONT></TD>
          <TD><FONT face="Arial, Helvetica, sans-serif" size=1>Used 
            differently by various implementations. May be used for 16 and 32 
            bit I/O.</FONT></TD></TR></TBODY></TABLE><BR></DIV>
      <P align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=1>By generating a single I/O write instruction to "base_address + 4", 
      the EPP controller will generate the necessary handshake signals and 
      strobes to transfer the data using an EPP Data_Write cycle. I/O 
      instructions to the base addresses, ports 0 through 2, will cause behavior 
      exactly as that as to a standard parallel port. This guarantees 
      compatibility with standard parallel port peripherals and printers. 
      Address cycles are generated when read or write I/O operations are 
      generated to "base_address + 3". </FONT></P>
      <P align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=1>Ports 5 through 7 are used differently by various hardware 
      implementations. These may be used to implement 16 or 32-bit software 
      interfaces, or used for configuration registers, or not used at all. For 
      example, the Warp Nine Engineering's' F/PortPlus card has only an 8-bit 
      data interface, but can be accessed using 32-bit I/O, for EPP data 
      operations. The ISA controller will intercept the 32- bit I/O and actually 
      generate 4 fast 8- bit I/O cycles. The first cycle will be to the 
      addressed I/O port using byte 0 (bits 0-7), the second cycle will be to 
      port+1 using byte 1, then port+2 using byte 2 and finally port+3 using 
      byte 3. These additional cycles are generated by hardware and are 
      transparent to the software. The total time for these four cycles will be 
      less than 4 independent 8 bit cycles. For example, the F/PortPlus card 
      (from Warp Nine Engineering) maps 4 I/O ports (offset 4 to 7) to the 
      internal EPP Data register. This enables the software to use 32-bit I/O 
      operations for EPP data transfer. Address cycles are still limited to 
      8-bit I/O. </FONT></P>
      <P align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=1>The ability to transfer data to or from the PC by the use of a 
      single instruction is what enables EPP mode parallel ports to transfer 
      data at ISA bus speeds. Rather than having the software implement an I/O 
      intensive software loop, a block of data can be transferred with a single 
      REP_IO instruction. Depending upon the host adapter port implementation 
      and the capability of the peripheral, an EPP port can transfer data from 
      500K bytes to nearly 2M bytes per second. This data transfer rate is more 
      than enough to enable network adapters, CD ROM, tape backup and other 
      peripherals to operate at nearly ISA bus performance levels. </FONT></P>
      <P align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=1>The EPP protocol and current implementations provide a high degree 
      of coupling between the peripheral driver and the peripheral. What this 
      means is the software driver is always able to determine and control the 
      state of communication to the peripheral at any given time. Intermixing of 
      read and write operations as well as block transfers are readily done. 
      This type of coupling is ideal for many register-oriented or real-time 
      controlled peripherals such as network adapters, data acquisition, 
      portable hard drives, and other devices.</FONT></P>
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