ecp mode.htm

并口的接口规范

          host.</FONT></TD></TR></TBODY></TABLE>
      <P align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=1>Figure 1 shows two forward data transfer cycles. When HostAck is 
      high it indicates that a data cycle is taking place. When HostAck is 
      asserted low, a command cycle is taking place and the data represents 
      either an RLE count or a Channel address. Bit 8, of the data byte is used 
      to indicate RLE vs. Channel address. If bit 8 is 0, then bits 1-7 
      represent a Run_Length Count (0-127). If bit 8 is 1, then bits 1-7 
      represent a Channel address (0-127). Figure 6 shows a data cycle followed 
      by a command cycle. </FONT></P>
      <P align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=1>Figure 2 shows a reverse channel command cycle followed by a 
      reverse channel data cycle. The I/O read or write strobes are not shown in 
      these figures. This is because the ECP FIFOs are used to decouple the ISA 
      data transfers, either DMA or programmed I/O, from the actual 
      host/peripheral data transfers. It is this decoupling of the transfer 
      states that makes the ECP protocol a "loosely coupled" protocol. The 
      software driver does not know the exact state of the data transfers. If a 
      large block is being transferred via DMA, the driver does not know if the 
      123rd byte is being transferred or the 342,201st byte. As in the case of 
      printers, the software may not care. The only concern is whether the 
      transfer was completed or not.</FONT></P>
      <P align=center><FONT face=Arial color=#000000><IMG height=176 
      src="ECP Mode.files/ecpfig1.gif" width=520><BR></FONT></P>
      <H3 align=center><FONT face=Arial color=#000000 size=1>Figure 1 -- ECP 
      Forward Data and Command Cycle<BR></FONT></H3>
      <P align=left><FONT face=Arial color=#000000 size=2>Forward Transfer phase 
      transistions:</FONT> 
      <OL>
        <LI>
        <DIV align=left><FONT face=Arial color=#000000 size=1>The host places 
        data on the data lines and indicates a data cycle by setting HostAck 
        high. </FONT></DIV>
        <LI>
        <DIV align=left><FONT face=Arial color=#000000 size=1>Host asserts 
        HostClk low to indicate valid data </FONT></DIV>
        <LI>
        <DIV align=left><FONT face=Arial color=#000000 size=1>Peripheral 
        acknowledges host by setting PeriphAck high </FONT></DIV>
        <LI>
        <DIV align=left><FONT face=Arial color=#000000 size=1>Host sets HostClk 
        high. This is the edge that should be used to clock the data in to the 
        peripheral. </FONT></DIV>
        <LI>
        <DIV align=left><FONT face=Arial color=#000000 size=1>Peripheral sets 
        PeriphAck low to indicate that it is ready for the next byte. 
        </FONT></DIV>
        <LI>
        <DIV align=left><FONT face=Arial color=#000000 size=1>The cycle repeats, 
        but this time it is a command cycle because HostAck is low. 
        </FONT></DIV></LI></OL>
      <P align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=1>NOTE: Since ECP transfers are loosely coupled, with a FIFO possibly 
      on both sides of the interface, it is important to note at which step the 
      data is considered "transferred". This point occurs at step 4, when the 
      HostClk goes high. At this time, the data should be clocked in to the 
      peripheral, and any data counters updated. There is a condition in the ECP 
      protocol that could cause the transfer to abort at between steps 3 and 4. 
      In this case the data should not be considered to have been transferred. 
      </FONT></P>
      <P align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=1>Figure 2 shows another of the differences between the ECP and EPP 
      protocols. With EPP, the software driver may intermix read and write 
      operations without any overhead or protocol handshaking. With the ECP 
      protocol, changes in the data direction must be negotiated. The host must 
      request a reverse channel transfer by asserting nReverseRequest and then 
      wait for the peripheral to acknowledge the request by asserting 
      nAckReverse. Only then can a reverse channel data transfer take place. In 
      addition, since the previous transfer may have been DMA driven, the host 
      software must either wait for the DMA to complete, or interrupt the DMA, 
      backflush the FIFO to determine the exact transferred byte count, and then 
      request the reverse channel. This adds a fair amount of overhead with 
      peripherals that require a lot of intermixed reading and writing of 
      registers or small buffers.</FONT></P>
      <P align=center><FONT face=Arial color=#000000 size=1>Figure 2 -- ECP 
      Reverse Data and Command Cycle</FONT></P>
      <P><FONT face=Arial color=#000000><FONT 
      face="Arial, Helvetica, sans-serif" size=2>Reverse Transfer phase 
      transistions:</FONT> <IMG src="ECP Mode.files/ecpfig2.gif"></FONT> 
      <OL style="COLOR: rgb(0,0,0)">
        <LI>
        <DIV align=left><FONT face=Arial color=#000000 size=1>The host requests 
        a reverse channel transfer by setting nReverseRequest low. </FONT></DIV>
        <LI>
        <DIV align=left><FONT face=Arial color=#000000 size=1>The peripheral 
        signals that it is OK to proceed by setting nAckReverse low 
</FONT></DIV>
        <LI>
        <DIV align=left><FONT face=Arial color=#000000 size=1>The peripheral 
        places data on the data lines and indicates a data cycle by setting 
        PeriphAck high. </FONT></DIV>
        <LI>
        <DIV align=left><FONT face=Arial color=#000000 size=1>Peripheral asserts 
        PeriphClk low to indicate valid data </FONT></DIV>
        <LI>
        <DIV align=left><FONT face=Arial color=#000000 size=1>Host acknowledges 
        by setting HostAck high </FONT></DIV>
        <LI>
        <DIV align=left><FONT face=Arial color=#000000 size=1>Peripheral sets 
        PeriphClk high. This is the edge that should be used to clock the data 
        in to the host. </FONT></DIV>
        <LI>
        <DIV align=left><FONT face=Arial color=#000000 size=1>Host sets HostAck 
        low to indicate that it is ready for the next byte. </FONT></DIV>
        <LI>
        <DIV align=left><FONT face=Arial color=#000000 size=1>The cycle repeats, 
        but this time it is a command cycle because PeriphAck is low. 
        </FONT></DIV></LI></OL>
      <H3><FONT face="Arial, Helvetica, sans-serif" color=#000000 size=2>ECP 
      Software and Register Interface</FONT></H3>
      <P align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=1>The Microsoft specification, "The IEEE 1284 Extended Capabilities 
      Port Protocol and ISA Interface Standard", defines a common register 
      interface for ISA based 1284 adapters with ECP. This specification also 
      defines a number of operational modes that the adapter can operate under. 
      Table 2 identifies these modes. </FONT></P>
      <H4 align=center><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=2>Table 2 -- ECR Register Modes</FONT></H4>
      <DIV align=center>
      <TABLE width=271 border=1>
        <TBODY>
        <TR>
          <TH align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=2>Mode</FONT></TH>
          <TH align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=2>Description</FONT></TH></TR>
        <TR>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>000</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>SPP mode</FONT></TD></TR>
        <TR>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>001</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>Bi-directional mode (Byte mode)</FONT></TD></TR>
        <TR>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>010</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>Fast Centronics</FONT></TD></TR>
        <TR>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>011</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>ECP Parallel Port mode</FONT></TD></TR>
        <TR>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>100</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>EPP Parallel Port mode <SUP>(note 
            1)</SUP></FONT></TD></TR>
        <TR>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>101</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>(reserved)</FONT></TD></TR>
        <TR>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>110</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>Test mode</FONT></TD></TR>
        <TR>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>111</FONT></TD>
          <TD align=middle><FONT face="Arial, Helvetica, sans-serif" 
            color=#000000 size=1>Configuration 
      mode</FONT></TD></TR></TBODY></TABLE><BR></DIV>
      <P align=left><FONT face=Arial color=#000000>(<FONT 
      face="Arial, Helvetica, sans-serif" size=1>note 1)</FONT></FONT><FONT 
      face="Arial, Helvetica, sans-serif" color=#000000 size=1> This mode is 
      implemented by the SMC FDC37C665/666 controller and is not defined by the 
      ECP specification. Most 1284 I/O controllers implement the EPP mode in a 
      similar fashion. </FONT></P>
      <P align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=1>The register model for an ECP port is similar to that of the 
      standard parallel port, but takes advantage of a significant design oddity 
      of the ISA bus architecture. In the IBM compatible PC architecture, only 
      the first 1024 I/O ports, or addresses, are used. This is the basic I/O 
      space of 0x000h to 0x3ffh. In order to address this range of addresses, 
      only 10 address bits are needed (AD0-9). In order to save cost, older PC's 
      only drove and decoded these address bits on the ISA bus and therefore 
      limited the available I/O space to these 1024 registers. Newer PC's, 
      actually drive and decode more address bits, enabling a larger available 
      I/O space. This creates, in effect, multiple "pages" of the first 1K I/O 
      ports. A software driver can access these pages by adding 1024 (0x400h hex 
      notation) to the base address being accessed. Therefore, addressing 
      addresses 0x378h and 0x778h can access 2 registers on two separate pages, 
      but be guaranteed not to interfere with any other installed ISA device. 
      The advantage is that by using this "aliasing" effect, new cards can have 
      "hidden" registers, thus expanding the available number of registers 
      available, and still maintain compatibility with older ISA cards that only 
      decode 10 address bits. </FONT></P>
      <P align=left><FONT face="Arial, Helvetica, sans-serif" color=#000000 
      size=1>The ECP register model takes advantage of this and defines 6 
      registers that only require 3 actual I/O ports. Table 9 identifies these 
      registers. Note that the register definition may be dependent upon the 
      current mode of operation. The ECR register is the most important aspect 
      of this register configuration. This is the register that is used to set 
      the current operational mode. Additionally, this register can be used by 
      software to determine if an ECP-capable port is installed in the PC. 
      Detection software can try to access any ECR registers by adding 0x402h to 
      the base address of the LPT ports identified in the BIOS LPT port 
      table.</FONT><FONT face=Arial color=#000000> </FONT></P>
      <H4 align=center><FONT face=Arial color=#000000 size=1>Table 3 -- ECP 
      Register Description</FONT></H4>
      <DIV align=center>
      <TABLE border=1>
        <TBODY>
        <TR>