p30f6010a.inc

AN1083, Sensorless BLDC Control with Back-EMF Filtering

         .equiv IC8CONH, _IC8CON+1              ;  sub-section below
;------------------------------------------------------------------------------
; 6b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     ICxCON : Input Capture x Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv ICSIDL, 0x000D

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv ICTMR, 0x0007
         .equiv ICI1, 0x0006
         .equiv ICI0, 0x0005
         .equiv ICOV, 0x0004
         .equiv ICBNE, 0x0003
         .equiv ICM2, 0x0002
         .equiv ICM1, 0x0001
         .equiv ICM0, 0x0000

;==============================================================================
;
; 7.  Output Compare Module Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 7a. SFR Definitions
;------------------------------------------------------------------------------
         .equiv OC1RSL, _OC1RS
         .equiv OC1RSH, _OC1RS+1
         .equiv OC1RL, _OC1R
         .equiv OC1RH, _OC1R+1
         .equiv OC1CONL, _OC1CON                ; See OCxCON description in
         .equiv OC1CONH, _OC1CON+1              ;  sub-section below
         .equiv OC2RSL, _OC2RS
         .equiv OC2RSH, _OC2RS+1
         .equiv OC2RL, _OC2R
         .equiv OC2RH, _OC2R+1
         .equiv OC2CONL, _OC2CON                ; See OCxCON description in
         .equiv OC2CONH, _OC2CON+1              ;  sub-section below
         .equiv OC3RSL, _OC3RS
         .equiv OC3RSH, _OC3RS+1
         .equiv OC3RL, _OC3R
         .equiv OC3RH, _OC3R+1
         .equiv OC3CONL, _OC3CON                ; See OCxCON description in
         .equiv OC3CONH, _OC3CON+1              ;  sub-section below
         .equiv OC4RSL, _OC4RS
         .equiv OC4RSH, _OC4RS+1
         .equiv OC4RL, _OC4R
         .equiv OC4RH, _OC4R+1
         .equiv OC4CONL, _OC4CON                ; See OCxCON description in
         .equiv OC4CONH, _OC4CON+1              ;  sub-section below
         .equiv OC5RSL, _OC5RS
         .equiv OC5RSH, _OC5RS+1
         .equiv OC5RL, _OC5R
         .equiv OC5RH, _OC5R+1
         .equiv OC5CONL, _OC5CON                ; See OCxCON description in
         .equiv OC5CONH, _OC5CON+1              ;  sub-section below
         .equiv OC6RSL, _OC6RS
         .equiv OC6RSH, _OC6RS+1
         .equiv OC6RL, _OC6R
         .equiv OC6RH, _OC6R+1
         .equiv OC6CONL, _OC6CON                ; See OCxCON description in
         .equiv OC6CONH, _OC6CON+1              ;  sub-section below
         .equiv OC7RSL, _OC7RS
         .equiv OC7RSH, _OC7RS+1
         .equiv OC7RL, _OC7R
         .equiv OC7RH, _OC7R+1
         .equiv OC7CONL, _OC7CON                ; See OCxCON description in
         .equiv OC7CONH, _OC7CON+1              ;  sub-section below
         .equiv OC8RSL, _OC8RS
         .equiv OC8RSH, _OC8RS+1
         .equiv OC8RL, _OC8R
         .equiv OC8RH, _OC8R+1
         .equiv OC8CONL, _OC8CON                ; See OCxCON description in
         .equiv OC8CONH, _OC8CON+1              ;  sub-section below

;------------------------------------------------------------------------------
; 7b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     OCxCON : Output Compare x Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv OCSIDL, 0x000D

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv OCFLT, 0x0004
         .equiv OCTSEL, 0x0003
         .equiv OCM2, 0x0002
         .equiv OCM1, 0x0001
         .equiv OCM0, 0x0000

;==============================================================================
;
; 8. Motor Control PWM Module Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 8a. SFR Definitions
;------------------------------------------------------------------------------
         .equiv PTCONL, _PTCON           ; See description for all registers
         .equiv PTCONH, _PTCON+1         ;  except PDCx registers, in section 8b
         .equiv PTMRL, _PTMR
         .equiv PTMRH, _PTMR+1
         .equiv PTPERL, _PTPER
         .equiv PTPERH, _PTPER+1
         .equiv SEVTCMPL, _SEVTCMP
         .equiv SEVTCMPH, _SEVTCMP+1
         .equiv PWMCON1L, _PWMCON1
         .equiv PWMCON1H, _PWMCON1+1
         .equiv PWMCON2L, _PWMCON2
         .equiv PWMCON2H, _PWMCON2+1
         .equiv DTCON1L, _DTCON1
         .equiv DTCON1H, _DTCON1+1
         .equiv DTCON2L, _DTCON2
         .equiv DTCON2H, _DTCON2+1
         .equiv FLTACONL, _FLTACON
         .equiv FLTACONH, _FLTACON+1
         .equiv FLTBCONL, _FLTBCON
         .equiv FLTBCONH, _FLTBCON+1
         .equiv OVDCONL, _OVDCON
         .equiv OVDCONH, _OVDCON+1
         .equiv PDC1L, _PDC1
         .equiv PDC1H, _PDC1+1
         .equiv PDC2L, _PDC2
         .equiv PDC2H, _PDC2+1
         .equiv PDC3L, _PDC3
         .equiv PDC3H, _PDC3+1
         .equiv PDC4L, _PDC4
         .equiv PDC4H, _PDC4+1

;------------------------------------------------------------------------------
; 8b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     PTCON : PWM Timebase Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv PTEN, 0x000F
         .equiv PTSIDL, 0x000D

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv PTOPS3, 0x0007
         .equiv PTOPS2, 0x0006
         .equiv PTOPS1, 0x0005
         .equiv PTOPS0, 0x0004
         .equiv PTCKPS1, 0x0003
         .equiv PTCKPS0, 0x0002
         .equiv PTMOD1, 0x0001
         .equiv PTMOD0, 0x0000

;------------------------------------------------------------------------------
;     PTMR : PWM Timebase Count Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv PTDIR, 0x000F

;------------------------------------------------------------------------------
;     SEVTCMP : Special Event Compare Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv SEVTDIR, 0x000F

;------------------------------------------------------------------------------
;     PWMCON1 : PWM Control Register 1
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv PMOD4, 0x000B
         .equiv PMOD3, 0x000A
         .equiv PMOD2, 0x0009
         .equiv PMOD1, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv PEN4H, 0x0007
         .equiv PEN3H, 0x0006
         .equiv PEN2H, 0x0005
         .equiv PEN1H, 0x0004
         .equiv PEN4L, 0x0003
         .equiv PEN3L, 0x0002
         .equiv PEN2L, 0x0001
         .equiv PEN1L, 0x0000

;------------------------------------------------------------------------------
;     PWMCON2 : PWM Control Register 2
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv SEVOPS3, 0x000B
         .equiv SEVOPS2, 0x000A
         .equiv SEVOPS1, 0x0009
         .equiv SEVOPS0, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv IUE, 0x0002
         .equiv OSYNC, 0x0001
         .equiv UDIS, 0x0000

;------------------------------------------------------------------------------
;     DTCON1 : Dead Time Control Register 1
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv DTBPS1, 0x000F
         .equiv DTBPS0, 0x000E
         .equiv DTB5, 0x000D
         .equiv DTB4, 0x000C
         .equiv DTB3, 0x000B
         .equiv DTB2, 0x000A
         .equiv DTB1, 0x0009
         .equiv DTB0, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv DTAPS1, 0x0007
         .equiv DTAPS0, 0x0006
         .equiv DTA5, 0x0005
         .equiv DTA4, 0x0004
         .equiv DTA3, 0x0003
         .equiv DTA2, 0x0002
         .equiv DTA1, 0x0001
         .equiv DTA0, 0x0000

;------------------------------------------------------------------------------
;     DTCON2 : Dead Time Control Register 2
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv DTS4A, 0x0007
         .equiv DTS4I, 0x0006
         .equiv DTS3A, 0x0005
         .equiv DTS3I, 0x0004
         .equiv DTS2A, 0x0003
         .equiv DTS2I, 0x0002
         .equiv DTS1A, 0x0001
         .equiv DTS1I, 0x0000

;------------------------------------------------------------------------------
;     FLTACON : Fault Input A Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv FAOV4H, 0x000F
         .equiv FAOV4L, 0x000E
         .equiv FAOV3H, 0x000D
         .equiv FAOV3L, 0x000C
         .equiv FAOV2H, 0x000B
         .equiv FAOV2L, 0x000A
         .equiv FAOV1H, 0x0009
         .equiv FAOV1L, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv FLTAM, 0x0007
         .equiv FAEN4, 0x0003
         .equiv FAEN3, 0x0002
         .equiv FAEN2, 0x0001
         .equiv FAEN1, 0x0000

;------------------------------------------------------------------------------
;     FLTBCON : Fault Input B Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv FBOV4H, 0x000F
         .equiv FBOV4L, 0x000E
         .equiv FBOV3H, 0x000D
         .equiv FBOV3L, 0x000C
         .equiv FBOV2H, 0x000B
         .equiv FBOV2L, 0x000A
         .equiv FBOV1H, 0x0009
         .equiv FBOV1L, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv FLTBM, 0x0007
         .equiv FBEN4, 0x0003
         .equiv FBEN3, 0x0002
         .equiv FBEN2, 0x0001
         .equiv FBEN1, 0x0000

;------------------------------------------------------------------------------
;     OVDCON : PWM Output Override Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv POVD4H, 0x000F
         .equiv POVD4L, 0x000E
         .equiv POVD3H, 0x000D
         .equiv POVD3L, 0x000C
         .equiv POVD2H, 0x000B
         .equiv POVD2L, 0x000A
         .equiv POVD1H, 0x0009
         .equiv POVD1L, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv POUT4H, 0x0007
         .equiv POUT4L, 0x0006
         .equiv POUT3H, 0x0005
         .equiv POUT3L, 0x0004
         .equiv POUT2H, 0x0003
         .equiv POUT2L, 0x0002
         .equiv POUT1H, 0x0001
         .equiv POUT1L, 0x0000

;==============================================================================
;
; 9. Inter-Integrated Circuit(I2C) Module Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 9a. SFR Definitions
;------------------------------------------------------------------------------
         .equiv I2CRCVL, _I2CRCV
         .equiv I2CRCVH, _I2CRCV+1
         .equiv I2CTRNL, _I2CTRN
         .equiv I2CTRNH, _I2CTRN+1
         .equiv I2CBRGL, _I2CBRG
         .equiv I2CBRGH, _I2CBRG+1
         .equiv I2CCONL, _I2CCON                ; See I2CCON description in
         .equiv I2CCONH, _I2CCON+1              ;  section 9b
         .equiv I2CSTATL, _I2CSTAT              ; See I2CSTAT description in
         .equiv I2CSTATH, _I2CSTAT+1            ;  section 9b
         .equiv I2CADDL, _I2CADD
         .equiv I2CADDH, _I2CADD+1

;------------------------------------------------------------------------------
; 9b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     I2CCON : I2C Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv I2CEN, 0x000F