📄 trian.tan.rpt
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; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; On ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; pll:inst5|altpll:altpll_component|_clk0 ; ; PLL output ; 256.02 MHz ; -1.833 ns ; -1.833 ns ; clk0 ; 16 ; 1 ; AUTO ; ;
; clk0 ; ; User Pin ; 16.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; cs ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; datinclk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; addrclk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; fswclk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pll:inst5|altpll:altpll_component|_clk0' ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
; -1.449 ns ; 186.74 MHz ( period = 5.355 ns ) ; sinwave:inst4|temp[1] ; sinwave:inst4|temp[3] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.645 ns ; 5.094 ns ;
; -1.448 ns ; 186.78 MHz ( period = 5.354 ns ) ; sinwave:inst4|temp[1] ; sinwave:inst4|clkout ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.645 ns ; 5.093 ns ;
; -1.443 ns ; 186.95 MHz ( period = 5.349 ns ) ; sinwave:inst4|temp[3] ; sinwave:inst4|temp[3] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.645 ns ; 5.088 ns ;
; -1.442 ns ; 186.99 MHz ( period = 5.348 ns ) ; sinwave:inst4|temp[3] ; sinwave:inst4|clkout ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.645 ns ; 5.087 ns ;
; -1.197 ns ; 195.96 MHz ( period = 5.103 ns ) ; sinwave:inst4|temp[1] ; sinwave:inst4|temp[1] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.645 ns ; 4.842 ns ;
; -1.191 ns ; 196.19 MHz ( period = 5.097 ns ) ; sinwave:inst4|temp[3] ; sinwave:inst4|temp[1] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.645 ns ; 4.836 ns ;
; -1.170 ns ; 197.01 MHz ( period = 5.076 ns ) ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_datain_reg3 ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_memory_reg3 ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.149 ns ; 4.319 ns ;
; -1.170 ns ; 197.01 MHz ( period = 5.076 ns ) ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_datain_reg2 ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_memory_reg2 ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.149 ns ; 4.319 ns ;
; -1.170 ns ; 197.01 MHz ( period = 5.076 ns ) ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_datain_reg1 ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_memory_reg1 ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.149 ns ; 4.319 ns ;
; -1.170 ns ; 197.01 MHz ( period = 5.076 ns ) ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_datain_reg0 ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_memory_reg0 ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.149 ns ; 4.319 ns ;
; -1.170 ns ; 197.01 MHz ( period = 5.076 ns ) ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_address_reg9 ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|q_a[3] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.149 ns ; 4.319 ns ;
; -1.170 ns ; 197.01 MHz ( period = 5.076 ns ) ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_address_reg8 ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|q_a[3] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.149 ns ; 4.319 ns ;
; -1.170 ns ; 197.01 MHz ( period = 5.076 ns ) ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_address_reg7 ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|q_a[3] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.149 ns ; 4.319 ns ;
; -1.170 ns ; 197.01 MHz ( period = 5.076 ns ) ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_address_reg6 ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|q_a[3] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.149 ns ; 4.319 ns ;
; -1.170 ns ; 197.01 MHz ( period = 5.076 ns ) ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_address_reg5 ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|q_a[3] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.149 ns ; 4.319 ns ;
; -1.170 ns ; 197.01 MHz ( period = 5.076 ns ) ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_address_reg4 ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|q_a[3] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.149 ns ; 4.319 ns ;
; -1.170 ns ; 197.01 MHz ( period = 5.076 ns ) ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_address_reg3 ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|q_a[3] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.149 ns ; 4.319 ns ;
; -1.170 ns ; 197.01 MHz ( period = 5.076 ns ) ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_address_reg2 ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|q_a[3] ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 3.906 ns ; 3.149 ns ; 4.319 ns ;
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