trian.tan.rpt

FPGA编写的三角波发生器

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+---------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+
; Type                                                   ; Slack     ; Required Time                    ; Actual Time                                    ; From                                                                            ; To                                                                                                 ; From Clock                              ; To Clock                                ; Failed Paths ;
+--------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+---------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+
; Worst-case tsu                                         ; N/A       ; None                             ; 4.517 ns                                       ; wren                                                                            ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a7~porta_we_reg ; --                                      ; clk0                                    ; 0            ;
; Worst-case tco                                         ; N/A       ; None                             ; 15.146 ns                                      ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|q_a[6] ; datout[6]                                                                                          ; cs                                      ; --                                      ; 0            ;
; Worst-case th                                          ; N/A       ; None                             ; 0.927 ns                                       ; wren                                                                            ; wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_we_reg ; --                                      ; cs                                      ; 0            ;
; Clock Setup: 'pll:inst5|altpll:altpll_component|_clk0' ; -1.449 ns ; 256.02 MHz ( period = 3.906 ns ) ; 186.74 MHz ( period = 5.355 ns )               ; sinwave:inst4|temp[1]                                                           ; sinwave:inst4|temp[3]                                                                              ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 114          ;
; Clock Setup: 'clk0'                                    ; 61.225 ns ; 16.00 MHz ( period = 62.500 ns ) ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fenpin:inst11|clk1                                                              ; fenpin:inst11|clk1                                                                                 ; clk0                                    ; clk0                                    ; 0            ;
; Clock Setup: 'cs'                                      ; N/A       ; None                             ; 186.74 MHz ( period = 5.355 ns )               ; sinwave:inst4|temp[1]                                                           ; sinwave:inst4|temp[3]                                                                              ; cs                                      ; cs                                      ; 0            ;
; Clock Setup: 'fswclk'                                  ; N/A       ; None                             ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fsw:inst16|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                         ; fsw:inst16|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                            ; fswclk                                  ; fswclk                                  ; 0            ;
; Clock Setup: 'addrclk'                                 ; N/A       ; None                             ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; dat:inst18|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                          ; dat:inst18|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                             ; addrclk                                 ; addrclk                                 ; 0            ;
; Clock Setup: 'datinclk'                                ; N/A       ; None                             ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                         ; datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                            ; datinclk                                ; datinclk                                ; 0            ;
; Clock Hold: 'clk0'                                     ; 1.223 ns  ; 16.00 MHz ( period = 62.500 ns ) ; N/A                                            ; fenpin:inst11|clk1                                                              ; fenpin:inst11|clk1                                                                                 ; clk0                                    ; clk0                                    ; 0            ;
; Clock Hold: 'pll:inst5|altpll:altpll_component|_clk0'  ; 1.314 ns  ; 256.02 MHz ( period = 3.906 ns ) ; N/A                                            ; sinwave:inst4|clkout                                                            ; sinwave:inst4|clkout                                                                               ; pll:inst5|altpll:altpll_component|_clk0 ; pll:inst5|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                           ;           ;                                  ;                                                ;                                                                                 ;                                                                                                    ;                                         ;                                         ; 114          ;
+--------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+---------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;