bianpin.v

来自「FPGA编写的三角波发生器」· Verilog 代码 · 共 10 行

module bianpin(counter,clk,fsw);
output[29:0]counter;
input clk;
input[27:0]fsw;
reg[29:0]counter;
always@(posedge clk)
begin
	counter=counter+fsw;
end
endmodule