trian.fit.qmsg

FPGA编写的三角波发生器

{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.346 ns register register " "Info: Estimated most critical path is register to register delay of 5.346 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sinwave:inst4\|temp\[1\] 1 REG LAB_X26_Y1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X26_Y1; Fanout = 3; REG Node = 'sinwave:inst4\|temp\[1\]'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sinwave:inst4|temp[1] } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.153 ns) + CELL(0.575 ns) 1.728 ns sinwave:inst4\|Add0~163COUT1_212 2 COMB LAB_X25_Y2 2 " "Info: 2: + IC(1.153 ns) + CELL(0.575 ns) = 1.728 ns; Loc. = LAB_X25_Y2; Fanout = 2; COMB Node = 'sinwave:inst4\|Add0~163COUT1_212'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.728 ns" { sinwave:inst4|temp[1] sinwave:inst4|Add0~163COUT1_212 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.808 ns sinwave:inst4\|Add0~169COUT1_214 3 COMB LAB_X25_Y2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.808 ns; Loc. = LAB_X25_Y2; Fanout = 2; COMB Node = 'sinwave:inst4\|Add0~169COUT1_214'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { sinwave:inst4|Add0~163COUT1_212 sinwave:inst4|Add0~169COUT1_214 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.888 ns sinwave:inst4\|Add0~165COUT1_216 4 COMB LAB_X25_Y2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.888 ns; Loc. = LAB_X25_Y2; Fanout = 2; COMB Node = 'sinwave:inst4\|Add0~165COUT1_216'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { sinwave:inst4|Add0~169COUT1_214 sinwave:inst4|Add0~165COUT1_216 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 2.496 ns sinwave:inst4\|Add0~170 5 COMB LAB_X25_Y2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.608 ns) = 2.496 ns; Loc. = LAB_X25_Y2; Fanout = 2; COMB Node = 'sinwave:inst4\|Add0~170'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.608 ns" { sinwave:inst4|Add0~165COUT1_216 sinwave:inst4|Add0~170 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.757 ns) + CELL(0.590 ns) 3.843 ns sinwave:inst4\|Equal0~141 6 COMB LAB_X26_Y1 1 " "Info: 6: + IC(0.757 ns) + CELL(0.590 ns) = 3.843 ns; Loc. = LAB_X26_Y1; Fanout = 1; COMB Node = 'sinwave:inst4\|Equal0~141'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.347 ns" { sinwave:inst4|Add0~170 sinwave:inst4|Equal0~141 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.064 ns) + CELL(0.590 ns) 4.497 ns sinwave:inst4\|Equal0~142 7 COMB LAB_X26_Y1 3 " "Info: 7: + IC(0.064 ns) + CELL(0.590 ns) = 4.497 ns; Loc. = LAB_X26_Y1; Fanout = 3; COMB Node = 'sinwave:inst4\|Equal0~142'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.654 ns" { sinwave:inst4|Equal0~141 sinwave:inst4|Equal0~142 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.309 ns) 5.346 ns sinwave:inst4\|clkout 8 REG LAB_X26_Y1 2 " "Info: 8: + IC(0.540 ns) + CELL(0.309 ns) = 5.346 ns; Loc. = LAB_X26_Y1; Fanout = 2; REG Node = 'sinwave:inst4\|clkout'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.849 ns" { sinwave:inst4|Equal0~142 sinwave:inst4|clkout } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.832 ns ( 52.97 % ) " "Info: Total cell delay = 2.832 ns ( 52.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.514 ns ( 47.03 % ) " "Info: Total interconnect delay = 2.514 ns ( 47.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.346 ns" { sinwave:inst4|temp[1] sinwave:inst4|Add0~163COUT1_212 sinwave:inst4|Add0~169COUT1_214 sinwave:inst4|Add0~165COUT1_216 sinwave:inst4|Add0~170 sinwave:inst4|Equal0~141 sinwave:inst4|Equal0~142 sinwave:inst4|clkout } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x14_y0 x27_y14 " "Info: The peak interconnect region extends from location x14_y0 to location x27_y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "6 " "Warning: Following 6 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "p33 GND " "Info: Pin p33 has GND driving its datain port" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 528 -608 -432 544 "p33" "" } } } } { "e:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "p33" } } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { p33 } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { p33 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "p35 GND " "Info: Pin p35 has GND driving its datain port" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 568 -632 -456 584 "p35" "" } } } } { "e:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "p35" } } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { p35 } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { p35 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "swt3 VCC " "Info: Pin swt3 has VCC driving its datain port" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 624 -632 -456 640 "swt3" "" } } } } { "e:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "swt3" } } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { swt3 } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { swt3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "swt2 VCC " "Info: Pin swt2 has VCC driving its datain port" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 664 -632 -456 680 "swt2" "" } } } } { "e:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "swt2" } } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { swt2 } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { swt2 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tcs GND " "Info: Pin tcs has GND driving its datain port" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 424 -648 -472 440 "tcs" "" } } } } { "e:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "tcs" } } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { tcs } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { tcs } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "treg GND " "Info: Pin treg has GND driving its datain port" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 464 -648 -472 480 "treg" "" } } } } { "e:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "treg" } } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { treg } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { treg } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 23 15:59:22 2007 " "Info: Processing ended: Thu Aug 23 15:59:22 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/altera/可调三角波/trian.fit.smsg " "Info: Generated suppressed messages file F:/altera/可调三角波/trian.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}