trian.map.qmsg

FPGA编写的三角波发生器

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram wave:inst\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"wave:inst\|altsyncram:altsyncram_component\"" {  } { { "wave.v" "altsyncram_component" { Text "F:/altera/可调三角波/wave.v" 71 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "wave:inst\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"wave:inst\|altsyncram:altsyncram_component\"" {  } { { "wave.v" "" { Text "F:/altera/可调三角波/wave.v" 71 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_aaa1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_aaa1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_aaa1 " "Info: Found entity 1: altsyncram_aaa1" {  } { { "db/altsyncram_aaa1.tdf" "" { Text "F:/altera/可调三角波/db/altsyncram_aaa1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_aaa1 wave:inst\|altsyncram:altsyncram_component\|altsyncram_aaa1:auto_generated " "Info: Elaborating entity \"altsyncram_aaa1\" for hierarchy \"wave:inst\|altsyncram:altsyncram_component\|altsyncram_aaa1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "chooseaddr chooseaddr:inst2 " "Info: Elaborating entity \"chooseaddr\" for hierarchy \"chooseaddr:inst2\"" {  } { { "trian.bdf" "inst2" { Schematic "F:/altera/可调三角波/trian.bdf" { { 464 736 904 592 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bianpin bianpin:inst3 " "Info: Elaborating entity \"bianpin\" for hierarchy \"bianpin:inst3\"" {  } { { "trian.bdf" "inst3" { Schematic "F:/altera/可调三角波/trian.bdf" { { 592 464 632 688 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fsw fsw:inst16 " "Info: Elaborating entity \"fsw\" for hierarchy \"fsw:inst16\"" {  } { { "trian.bdf" "inst16" { Schematic "F:/altera/可调三角波/trian.bdf" { { 592 72 216 672 "inst16" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/program files/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/program files/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "lpm_shiftreg.tdf" "" { Text "e:/program files/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf" 37 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_shiftreg fsw:inst16\|lpm_shiftreg:lpm_shiftreg_component " "Info: Elaborating entity \"lpm_shiftreg\" for hierarchy \"fsw:inst16\|lpm_shiftreg:lpm_shiftreg_component\"" {  } { { "fsw.v" "lpm_shiftreg_component" { Text "F:/altera/可调三角波/fsw.v" 63 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "fsw:inst16\|lpm_shiftreg:lpm_shiftreg_component " "Info: Elaborated megafunction instantiation \"fsw:inst16\|lpm_shiftreg:lpm_shiftreg_component\"" {  } { { "fsw.v" "" { Text "F:/altera/可调三角波/fsw.v" 63 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dat dat:inst18 " "Info: Elaborating entity \"dat\" for hierarchy \"dat:inst18\"" {  } { { "trian.bdf" "inst18" { Schematic "F:/altera/可调三角波/trian.bdf" { { 480 80 224 560 "inst18" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_shiftreg dat:inst18\|lpm_shiftreg:lpm_shiftreg_component " "Info: Elaborating entity \"lpm_shiftreg\" for hierarchy \"dat:inst18\|lpm_shiftreg:lpm_shiftreg_component\"" {  } { { "dat.v" "lpm_shiftreg_component" { Text "F:/altera/可调三角波/dat.v" 63 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dat:inst18\|lpm_shiftreg:lpm_shiftreg_component " "Info: Elaborated megafunction instantiation \"dat:inst18\|lpm_shiftreg:lpm_shiftreg_component\"" {  } { { "dat.v" "" { Text "F:/altera/可调三角波/dat.v" 63 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "datin datin:inst1 " "Info: Elaborating entity \"datin\" for hierarchy \"datin:inst1\"" {  } { { "trian.bdf" "inst1" { Schematic "F:/altera/可调三角波/trian.bdf" { { 376 80 224 456 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_shiftreg datin:inst1\|lpm_shiftreg:lpm_shiftreg_component " "Info: Elaborating entity \"lpm_shiftreg\" for hierarchy \"datin:inst1\|lpm_shiftreg:lpm_shiftreg_component\"" {  } { { "datin.v" "lpm_shiftreg_component" { Text "F:/altera/可调三角波/datin.v" 63 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "datin:inst1\|lpm_shiftreg:lpm_shiftreg_component " "Info: Elaborated megafunction instantiation \"datin:inst1\|lpm_shiftreg:lpm_shiftreg_component\"" {  } { { "datin.v" "" { Text "F:/altera/可调三角波/datin.v" 63 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "p33 GND " "Warning: Pin \"p33\" stuck at GND" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 528 -608 -432 544 "p33" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "p35 GND " "Warning: Pin \"p35\" stuck at GND" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 568 -632 -456 584 "p35" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "swt3 VCC " "Warning: Pin \"swt3\" stuck at VCC" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 624 -632 -456 640 "swt3" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "swt2 VCC " "Warning: Pin \"swt2\" stuck at VCC" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 664 -632 -456 680 "swt2" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "tcs GND " "Warning: Pin \"tcs\" stuck at GND" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 424 -648 -472 440 "tcs" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "treg GND " "Warning: Pin \"treg\" stuck at GND" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 464 -648 -472 480 "treg" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "150 " "Info: Implemented 150 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "115 " "Info: Implemented 115 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 23 15:59:12 2007 " "Info: Processing ended: Thu Aug 23 15:59:12 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}