trian.tan.qmsg

FPGA编写的三角波发生器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "cs register sinwave:inst4\|temp\[1\] register sinwave:inst4\|temp\[3\] 186.74 MHz 5.355 ns Internal " "Info: Clock \"cs\" has Internal fmax of 186.74 MHz between source register \"sinwave:inst4\|temp\[1\]\" and destination register \"sinwave:inst4\|temp\[3\]\" (period= 5.355 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.094 ns + Longest register register " "Info: + Longest register to register delay is 5.094 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sinwave:inst4\|temp\[1\] 1 REG LC_X26_Y1_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y1_N7; Fanout = 3; REG Node = 'sinwave:inst4\|temp\[1\]'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sinwave:inst4|temp[1] } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.243 ns) + CELL(0.432 ns) 1.675 ns sinwave:inst4\|Add0~163COUT1_212 2 COMB LC_X25_Y2_N6 2 " "Info: 2: + IC(1.243 ns) + CELL(0.432 ns) = 1.675 ns; Loc. = LC_X25_Y2_N6; Fanout = 2; COMB Node = 'sinwave:inst4\|Add0~163COUT1_212'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.675 ns" { sinwave:inst4|temp[1] sinwave:inst4|Add0~163COUT1_212 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.755 ns sinwave:inst4\|Add0~169COUT1_214 3 COMB LC_X25_Y2_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.755 ns; Loc. = LC_X25_Y2_N7; Fanout = 2; COMB Node = 'sinwave:inst4\|Add0~169COUT1_214'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { sinwave:inst4|Add0~163COUT1_212 sinwave:inst4|Add0~169COUT1_214 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.835 ns sinwave:inst4\|Add0~165COUT1_216 4 COMB LC_X25_Y2_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.835 ns; Loc. = LC_X25_Y2_N8; Fanout = 2; COMB Node = 'sinwave:inst4\|Add0~165COUT1_216'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { sinwave:inst4|Add0~169COUT1_214 sinwave:inst4|Add0~165COUT1_216 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 2.093 ns sinwave:inst4\|Add0~171 5 COMB LC_X25_Y2_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 2.093 ns; Loc. = LC_X25_Y2_N9; Fanout = 6; COMB Node = 'sinwave:inst4\|Add0~171'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { sinwave:inst4|Add0~165COUT1_216 sinwave:inst4|Add0~171 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.772 ns sinwave:inst4\|Add0~174 6 COMB LC_X25_Y1_N1 2 " "Info: 6: + IC(0.000 ns) + CELL(0.679 ns) = 2.772 ns; Loc. = LC_X25_Y1_N1; Fanout = 2; COMB Node = 'sinwave:inst4\|Add0~174'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.679 ns" { sinwave:inst4|Add0~171 sinwave:inst4|Add0~174 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.693 ns) + CELL(0.590 ns) 4.055 ns sinwave:inst4\|Equal0~141 7 COMB LC_X26_Y1_N5 1 " "Info: 7: + IC(0.693 ns) + CELL(0.590 ns) = 4.055 ns; Loc. = LC_X26_Y1_N5; Fanout = 1; COMB Node = 'sinwave:inst4\|Equal0~141'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.283 ns" { sinwave:inst4|Add0~174 sinwave:inst4|Equal0~141 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 4.351 ns sinwave:inst4\|Equal0~142 8 COMB LC_X26_Y1_N6 3 " "Info: 8: + IC(0.182 ns) + CELL(0.114 ns) = 4.351 ns; Loc. = LC_X26_Y1_N6; Fanout = 3; COMB Node = 'sinwave:inst4\|Equal0~142'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { sinwave:inst4|Equal0~141 sinwave:inst4|Equal0~142 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.309 ns) 5.094 ns sinwave:inst4\|temp\[3\] 9 REG LC_X26_Y1_N0 3 " "Info: 9: + IC(0.434 ns) + CELL(0.309 ns) = 5.094 ns; Loc. = LC_X26_Y1_N0; Fanout = 3; REG Node = 'sinwave:inst4\|temp\[3\]'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.743 ns" { sinwave:inst4|Equal0~142 sinwave:inst4|temp[3] } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.542 ns ( 49.90 % ) " "Info: Total cell delay = 2.542 ns ( 49.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.552 ns ( 50.10 % ) " "Info: Total interconnect delay = 2.552 ns ( 50.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.094 ns" { sinwave:inst4|temp[1] sinwave:inst4|Add0~163COUT1_212 sinwave:inst4|Add0~169COUT1_214 sinwave:inst4|Add0~165COUT1_216 sinwave:inst4|Add0~171 sinwave:inst4|Add0~174 sinwave:inst4|Equal0~141 sinwave:inst4|Equal0~142 sinwave:inst4|temp[3] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.094 ns" { sinwave:inst4|temp[1] sinwave:inst4|Add0~163COUT1_212 sinwave:inst4|Add0~169COUT1_214 sinwave:inst4|Add0~165COUT1_216 sinwave:inst4|Add0~171 sinwave:inst4|Add0~174 sinwave:inst4|Equal0~141 sinwave:inst4|Equal0~142 sinwave:inst4|temp[3] } { 0.000ns 1.243ns 0.000ns 0.000ns 0.000ns 0.000ns 0.693ns 0.182ns 0.434ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.258ns 0.679ns 0.590ns 0.114ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cs destination 9.381 ns + Shortest register " "Info: + Shortest clock path from clock \"cs\" to destination register is 9.381 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns cs 1 CLK PIN_108 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_108; Fanout = 12; CLK Node = 'cs'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cs } "NODE_NAME" } } { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 320 -208 -40 336 "cs" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.292 ns) 5.261 ns inst10~11 2 COMB LC_X8_Y6_N4 68 " "Info: 2: + IC(3.500 ns) + CELL(0.292 ns) = 5.261 ns; Loc. = LC_X8_Y6_N4; Fanout = 68; COMB Node = 'inst10~11'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.792 ns" { cs inst10~11 } "NODE_NAME" } } { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 280 712 776 328 "inst10" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.409 ns) + CELL(0.711 ns) 9.381 ns sinwave:inst4\|temp\[3\] 3 REG LC_X26_Y1_N0 3 " "Info: 3: + IC(3.409 ns) + CELL(0.711 ns) = 9.381 ns; Loc. = LC_X26_Y1_N0; Fanout = 3; REG Node = 'sinwave:inst4\|temp\[3\]'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.120 ns" { inst10~11 sinwave:inst4|temp[3] } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.472 ns ( 26.35 % ) " "Info: Total cell delay = 2.472 ns ( 26.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.909 ns ( 73.65 % ) " "Info: Total interconnect delay = 6.909 ns ( 73.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.381 ns" { cs inst10~11 sinwave:inst4|temp[3] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "9.381 ns" { cs cs~out0 inst10~11 sinwave:inst4|temp[3] } { 0.000ns 0.000ns 3.500ns 3.409ns } { 0.000ns 1.469ns 0.292ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cs source 9.381 ns - Longest register " "Info: - Longest clock path from clock \"cs\" to source register is 9.381 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns cs 1 CLK PIN_108 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_108; Fanout = 12; CLK Node = 'cs'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cs } "NODE_NAME" } } { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 320 -208 -40 336 "cs" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.292 ns) 5.261 ns inst10~11 2 COMB LC_X8_Y6_N4 68 " "Info: 2: + IC(3.500 ns) + CELL(0.292 ns) = 5.261 ns; Loc. = LC_X8_Y6_N4; Fanout = 68; COMB Node = 'inst10~11'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.792 ns" { cs inst10~11 } "NODE_NAME" } } { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 280 712 776 328 "inst10" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.409 ns) + CELL(0.711 ns) 9.381 ns sinwave:inst4\|temp\[1\] 3 REG LC_X26_Y1_N7 3 " "Info: 3: + IC(3.409 ns) + CELL(0.711 ns) = 9.381 ns; Loc. = LC_X26_Y1_N7; Fanout = 3; REG Node = 'sinwave:inst4\|temp\[1\]'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.120 ns" { inst10~11 sinwave:inst4|temp[1] } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.472 ns ( 26.35 % ) " "Info: Total cell delay = 2.472 ns ( 26.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.909 ns ( 73.65 % ) " "Info: Total interconnect delay = 6.909 ns ( 73.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.381 ns" { cs inst10~11 sinwave:inst4|temp[1] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "9.381 ns" { cs cs~out0 inst10~11 sinwave:inst4|temp[1] } { 0.000ns 0.000ns 3.500ns 3.409ns } { 0.000ns 1.469ns 0.292ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.381 ns" { cs inst10~11 sinwave:inst4|temp[3] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "9.381 ns" { cs cs~out0 inst10~11 sinwave:inst4|temp[3] } { 0.000ns 0.000ns 3.500ns 3.409ns } { 0.000ns 1.469ns 0.292ns 0.711ns } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.381 ns" { cs inst10~11 sinwave:inst4|temp[1] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "9.381 ns" { cs cs~out0 inst10~11 sinwave:inst4|temp[1] } { 0.000ns 0.000ns 3.500ns 3.409ns } { 0.000ns 1.469ns 0.292ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.094 ns" { sinwave:inst4|temp[1] sinwave:inst4|Add0~163COUT1_212 sinwave:inst4|Add0~169COUT1_214 sinwave:inst4|Add0~165COUT1_216 sinwave:inst4|Add0~171 sinwave:inst4|Add0~174 sinwave:inst4|Equal0~141 sinwave:inst4|Equal0~142 sinwave:inst4|temp[3] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.094 ns" { sinwave:inst4|temp[1] sinwave:inst4|Add0~163COUT1_212 sinwave:inst4|Add0~169COUT1_214 sinwave:inst4|Add0~165COUT1_216 sinwave:inst4|Add0~171 sinwave:inst4|Add0~174 sinwave:inst4|Equal0~141 sinwave:inst4|Equal0~142 sinwave:inst4|temp[3] } { 0.000ns 1.243ns 0.000ns 0.000ns 0.000ns 0.000ns 0.693ns 0.182ns 0.434ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.258ns 0.679ns 0.590ns 0.114ns 0.309ns } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.381 ns" { cs inst10~11 sinwave:inst4|temp[3] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "9.381 ns" { cs cs~out0 inst10~11 sinwave:inst4|temp[3] } { 0.000ns 0.000ns 3.500ns 3.409ns } { 0.000ns 1.469ns 0.292ns 0.711ns } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.381 ns" { cs inst10~11 sinwave:inst4|temp[1] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "9.381 ns" { cs cs~out0 inst10~11 sinwave:inst4|temp[1] } { 0.000ns 0.000ns 3.500ns 3.409ns } { 0.000ns 1.469ns 0.292ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "datinclk register register datin:inst1\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[4\] datin:inst1\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[5\] 275.03 MHz Internal " "Info: Clock \"datinclk\" Internal fmax is restricted to 275.03 MHz between source register \"datin:inst1\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[4\]\" and destination register \"datin:inst1\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[5\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.831 ns + Longest register register " "Info: + Longest register to register delay is 0.831 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns datin:inst1\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[4\] 1 REG LC_X12_Y7_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y7_N5; Fanout = 2; REG Node = 'datin:inst1\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[4\]'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] } "NODE_NAME" } } { "lpm_shiftreg.tdf" "" { Text "e:/program files/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.309 ns) 0.831 ns datin:inst1\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[5\] 2 REG LC_X12_Y7_N9 2 " "Info: 2: + IC(0.522 ns) + CELL(0.309 ns) = 0.831 ns; Loc. = LC_X12_Y7_N9; Fanout = 2; REG Node = 'datin:inst1\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[5\]'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.831 ns" { datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[5] } "NODE_NAME" } } { "lpm_shiftreg.tdf" "" { Text "e:/program files/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 37.18 % ) " "Info: Total cell delay = 0.309 ns ( 37.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.522 ns ( 62.82 % ) " "Info: Total interconnect delay = 0.522 ns ( 62.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.831 ns" { datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[5] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "0.831 ns" { datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[5] } { 0.000ns 0.522ns } { 0.000ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "datinclk destination 6.330 ns + Shortest register " "Info: + Shortest clock path from clock \"datinclk\" to destination register is 6.330 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns datinclk 1 CLK PIN_97 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_97; Fanout = 8; CLK Node = 'datinclk'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { datinclk } "NODE_NAME" } } { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 392 -248 -80 408 "datinclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.150 ns) + CELL(0.711 ns) 6.330 ns datin:inst1\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[5\] 2 REG LC_X12_Y7_N9 2 " "Info: 2: + IC(4.150 ns) + CELL(0.711 ns) = 6.330 ns; Loc. = LC_X12_Y7_N9; Fanout = 2; REG Node = 'datin:inst1\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[5\]'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.861 ns" { datinclk datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[5] } "NODE_NAME" } } { "lpm_shiftreg.tdf" "" { Text "e:/program files/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 34.44 % ) " "Info: Total cell delay = 2.180 ns ( 34.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.150 ns ( 65.56 % ) " "Info: Total interconnect delay = 4.150 ns ( 65.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.330 ns" { datinclk datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[5] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.330 ns" { datinclk datinclk~out0 datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[5] } { 0.000ns 0.000ns 4.150ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "datinclk source 6.330 ns - Longest register " "Info: - Longest clock path from clock \"datinclk\" to source register is 6.330 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns datinclk 1 CLK PIN_97 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_97; Fanout = 8; CLK Node = 'datinclk'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { datinclk } "NODE_NAME" } } { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 392 -248 -80 408 "datinclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.150 ns) + CELL(0.711 ns) 6.330 ns datin:inst1\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[4\] 2 REG LC_X12_Y7_N5 2 " "Info: 2: + IC(4.150 ns) + CELL(0.711 ns) = 6.330 ns; Loc. = LC_X12_Y7_N5; Fanout = 2; REG Node = 'datin:inst1\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[4\]'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.861 ns" { datinclk datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] } "NODE_NAME" } } { "lpm_shiftreg.tdf" "" { Text "e:/program files/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 34.44 % ) " "Info: Total cell delay = 2.180 ns ( 34.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.150 ns ( 65.56 % ) " "Info: Total interconnect delay = 4.150 ns ( 65.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.330 ns" { datinclk datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.330 ns" { datinclk datinclk~out0 datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] } { 0.000ns 0.000ns 4.150ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.330 ns