trian.tan.qmsg

FPGA编写的三角波发生器

{ "Info" "ITDB_FULL_SLACK_RESULT" "pll:inst5\|altpll:altpll_component\|_clk0 register sinwave:inst4\|temp\[1\] register sinwave:inst4\|temp\[3\] -1.449 ns " "Info: Slack time is -1.449 ns for clock \"pll:inst5\|altpll:altpll_component\|_clk0\" between source register \"sinwave:inst4\|temp\[1\]\" and destination register \"sinwave:inst4\|temp\[3\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "186.74 MHz 5.355 ns " "Info: Fmax is 186.74 MHz (period= 5.355 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "3.645 ns + Largest register register " "Info: + Largest register to register requirement is 3.645 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "3.906 ns + " "Info: + Setup relationship between source and destination is 3.906 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 3.906 ns " "Info: + Latch edge is 3.906 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll:inst5\|altpll:altpll_component\|_clk0 3.906 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"pll:inst5\|altpll:altpll_component\|_clk0\" is 3.906 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Destination 0.000 ns 0.000 degrees " "Info: Clock offset from Destination is based on specified offset of 0.000 ns and phase shift of 0.000 degrees of the derived clock" {  } {  } 0 0 "Clock offset from %1!s! is based on specified offset of %2!s! and phase shift of %3!s! of the derived clock" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll:inst5\|altpll:altpll_component\|_clk0 3.906 ns 0.000 ns  50 " "Info: Clock period of Source clock \"pll:inst5\|altpll:altpll_component\|_clk0\" is 3.906 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Source 0.000 ns 0.000 degrees " "Info: Clock offset from Source is based on specified offset of 0.000 ns and phase shift of 0.000 degrees of the derived clock" {  } {  } 0 0 "Clock offset from %1!s! is based on specified offset of %2!s! and phase shift of %3!s! of the derived clock" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst5\|altpll:altpll_component\|_clk0 destination 6.363 ns + Shortest register " "Info: + Shortest clock path from clock \"pll:inst5\|altpll:altpll_component\|_clk0\" to destination register is 6.363 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst5\|altpll:altpll_component\|_clk0 1 CLK PLL_1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 2; CLK Node = 'pll:inst5\|altpll:altpll_component\|_clk0'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll:inst5|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/program files/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.129 ns) + CELL(0.114 ns) 2.243 ns inst10~11 2 COMB LC_X8_Y6_N4 68 " "Info: 2: + IC(2.129 ns) + CELL(0.114 ns) = 2.243 ns; Loc. = LC_X8_Y6_N4; Fanout = 68; COMB Node = 'inst10~11'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.243 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 } "NODE_NAME" } } { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 280 712 776 328 "inst10" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.409 ns) + CELL(0.711 ns) 6.363 ns sinwave:inst4\|temp\[3\] 3 REG LC_X26_Y1_N0 3 " "Info: 3: + IC(3.409 ns) + CELL(0.711 ns) = 6.363 ns; Loc. = LC_X26_Y1_N0; Fanout = 3; REG Node = 'sinwave:inst4\|temp\[3\]'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.120 ns" { inst10~11 sinwave:inst4|temp[3] } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.825 ns ( 12.97 % ) " "Info: Total cell delay = 0.825 ns ( 12.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.538 ns ( 87.03 % ) " "Info: Total interconnect delay = 5.538 ns ( 87.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[3] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[3] } { 0.000ns 2.129ns 3.409ns } { 0.000ns 0.114ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:inst5\|altpll:altpll_component\|_clk0 source 6.363 ns - Longest register " "Info: - Longest clock path from clock \"pll:inst5\|altpll:altpll_component\|_clk0\" to source register is 6.363 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:inst5\|altpll:altpll_component\|_clk0 1 CLK PLL_1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 2; CLK Node = 'pll:inst5\|altpll:altpll_component\|_clk0'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll:inst5|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/program files/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.129 ns) + CELL(0.114 ns) 2.243 ns inst10~11 2 COMB LC_X8_Y6_N4 68 " "Info: 2: + IC(2.129 ns) + CELL(0.114 ns) = 2.243 ns; Loc. = LC_X8_Y6_N4; Fanout = 68; COMB Node = 'inst10~11'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.243 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 } "NODE_NAME" } } { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 280 712 776 328 "inst10" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.409 ns) + CELL(0.711 ns) 6.363 ns sinwave:inst4\|temp\[1\] 3 REG LC_X26_Y1_N7 3 " "Info: 3: + IC(3.409 ns) + CELL(0.711 ns) = 6.363 ns; Loc. = LC_X26_Y1_N7; Fanout = 3; REG Node = 'sinwave:inst4\|temp\[1\]'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.120 ns" { inst10~11 sinwave:inst4|temp[1] } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.825 ns ( 12.97 % ) " "Info: Total cell delay = 0.825 ns ( 12.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.538 ns ( 87.03 % ) " "Info: Total interconnect delay = 5.538 ns ( 87.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[1] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[1] } { 0.000ns 2.129ns 3.409ns } { 0.000ns 0.114ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[3] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[3] } { 0.000ns 2.129ns 3.409ns } { 0.000ns 0.114ns 0.711ns } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[1] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[1] } { 0.000ns 2.129ns 3.409ns } { 0.000ns 0.114ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[3] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[3] } { 0.000ns 2.129ns 3.409ns } { 0.000ns 0.114ns 0.711ns } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[1] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[1] } { 0.000ns 2.129ns 3.409ns } { 0.000ns 0.114ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.094 ns - Longest register register " "Info: - Longest register to register delay is 5.094 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sinwave:inst4\|temp\[1\] 1 REG LC_X26_Y1_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y1_N7; Fanout = 3; REG Node = 'sinwave:inst4\|temp\[1\]'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sinwave:inst4|temp[1] } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.243 ns) + CELL(0.432 ns) 1.675 ns sinwave:inst4\|Add0~163COUT1_212 2 COMB LC_X25_Y2_N6 2 " "Info: 2: + IC(1.243 ns) + CELL(0.432 ns) = 1.675 ns; Loc. = LC_X25_Y2_N6; Fanout = 2; COMB Node = 'sinwave:inst4\|Add0~163COUT1_212'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.675 ns" { sinwave:inst4|temp[1] sinwave:inst4|Add0~163COUT1_212 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.755 ns sinwave:inst4\|Add0~169COUT1_214 3 COMB LC_X25_Y2_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.755 ns; Loc. = LC_X25_Y2_N7; Fanout = 2; COMB Node = 'sinwave:inst4\|Add0~169COUT1_214'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { sinwave:inst4|Add0~163COUT1_212 sinwave:inst4|Add0~169COUT1_214 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.835 ns sinwave:inst4\|Add0~165COUT1_216 4 COMB LC_X25_Y2_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.835 ns; Loc. = LC_X25_Y2_N8; Fanout = 2; COMB Node = 'sinwave:inst4\|Add0~165COUT1_216'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { sinwave:inst4|Add0~169COUT1_214 sinwave:inst4|Add0~165COUT1_216 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 2.093 ns sinwave:inst4\|Add0~171 5 COMB LC_X25_Y2_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 2.093 ns; Loc. = LC_X25_Y2_N9; Fanout = 6; COMB Node = 'sinwave:inst4\|Add0~171'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { sinwave:inst4|Add0~165COUT1_216 sinwave:inst4|Add0~171 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.772 ns sinwave:inst4\|Add0~174 6 COMB LC_X25_Y1_N1 2 " "Info: 6: + IC(0.000 ns) + CELL(0.679 ns) = 2.772 ns; Loc. = LC_X25_Y1_N1; Fanout = 2; COMB Node = 'sinwave:inst4\|Add0~174'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.679 ns" { sinwave:inst4|Add0~171 sinwave:inst4|Add0~174 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.693 ns) + CELL(0.590 ns) 4.055 ns sinwave:inst4\|Equal0~141 7 COMB LC_X26_Y1_N5 1 " "Info: 7: + IC(0.693 ns) + CELL(0.590 ns) = 4.055 ns; Loc. = LC_X26_Y1_N5; Fanout = 1; COMB Node = 'sinwave:inst4\|Equal0~141'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.283 ns" { sinwave:inst4|Add0~174 sinwave:inst4|Equal0~141 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 4.351 ns sinwave:inst4\|Equal0~142 8 COMB LC_X26_Y1_N6 3 " "Info: 8: + IC(0.182 ns) + CELL(0.114 ns) = 4.351 ns; Loc. = LC_X26_Y1_N6; Fanout = 3; COMB Node = 'sinwave:inst4\|Equal0~142'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { sinwave:inst4|Equal0~141 sinwave:inst4|Equal0~142 } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.309 ns) 5.094 ns sinwave:inst4\|temp\[3\] 9 REG LC_X26_Y1_N0 3 " "Info: 9: + IC(0.434 ns) + CELL(0.309 ns) = 5.094 ns; Loc. = LC_X26_Y1_N0; Fanout = 3; REG Node = 'sinwave:inst4\|temp\[3\]'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.743 ns" { sinwave:inst4|Equal0~142 sinwave:inst4|temp[3] } "NODE_NAME" } } { "sinwave.v" "" { Text "F:/altera/可调三角波/sinwave.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.542 ns ( 49.90 % ) " "Info: Total cell delay = 2.542 ns ( 49.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.552 ns ( 50.10 % ) " "Info: Total interconnect delay = 2.552 ns ( 50.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.094 ns" { sinwave:inst4|temp[1] sinwave:inst4|Add0~163COUT1_212 sinwave:inst4|Add0~169COUT1_214 sinwave:inst4|Add0~165COUT1_216 sinwave:inst4|Add0~171 sinwave:inst4|Add0~174 sinwave:inst4|Equal0~141 sinwave:inst4|Equal0~142 sinwave:inst4|temp[3] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.094 ns" { sinwave:inst4|temp[1] sinwave:inst4|Add0~163COUT1_212 sinwave:inst4|Add0~169COUT1_214 sinwave:inst4|Add0~165COUT1_216 sinwave:inst4|Add0~171 sinwave:inst4|Add0~174 sinwave:inst4|Equal0~141 sinwave:inst4|Equal0~142 sinwave:inst4|temp[3] } { 0.000ns 1.243ns 0.000ns 0.000ns 0.000ns 0.000ns 0.693ns 0.182ns 0.434ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.258ns 0.679ns 0.590ns 0.114ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[3] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[3] } { 0.000ns 2.129ns 3.409ns } { 0.000ns 0.114ns 0.711ns } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[1] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.363 ns" { pll:inst5|altpll:altpll_component|_clk0 inst10~11 sinwave:inst4|temp[1] } { 0.000ns 2.129ns 3.409ns } { 0.000ns 0.114ns 0.711ns } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.094 ns" { sinwave:inst4|temp[1] sinwave:inst4|Add0~163COUT1_212 sinwave:inst4|Add0~169COUT1_214 sinwave:inst4|Add0~165COUT1_216 sinwave:inst4|Add0~171 sinwave:inst4|Add0~174 sinwave:inst4|Equal0~141 sinwave:inst4|Equal0~142 sinwave:inst4|temp[3] } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.094 ns" { sinwave:inst4|temp[1] sinwave:inst4|Add0~163COUT1_212 sinwave:inst4|Add0~169COUT1_214 sinwave:inst4|Add0~165COUT1_216 sinwave:inst4|Add0~171 sinwave:inst4|Add0~174 sinwave:inst4|Equal0~141 sinwave:inst4|Equal0~142 sinwave:inst4|temp[3] } { 0.000ns 1.243ns 0.000ns 0.000ns 0.000ns 0.000ns 0.693ns 0.182ns 0.434ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.258ns 0.679ns 0.590ns 0.114ns 0.309ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'pll:inst5\|altpll:altpll_component\|_clk0' 114 " "Warning: Can't achieve timing requirement Clock Setup: 'pll:inst5\|altpll:altpll_component\|_clk0' along 114 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk0 register fenpin:inst11\|clk1 register fenpin:inst11\|clk1 61.225 ns " "Info: Slack time is 61.225 ns for clock \"clk0\" between source register \"fenpin:inst11\|clk1\" and destination register \"fenpin:inst11\|clk1\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "275.03 MHz " "Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits" {  } {  } 0 0 "Fmax is restricted to %1!s! due to tcl and tch limits" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "62.239 ns + Largest register register " "Info: + Largest register to register requirement is 62.239 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "62.500 ns + " "Info: + Setup relationship between source and destination is 62.500 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 62.500 ns " "Info: + Latch edge is 62.500 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk0 62.500 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk0\" is 62.500 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk0 62.500 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk0\" is 62.500 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 2.743 ns + Shortest register " "Info: + Shortest clock path from clock \"clk0\" to destination register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'clk0'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 248 -768 -600 264 "clk0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns fenpin:inst11\|clk1 2 REG LC_X26_Y3_N2 2 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X26_Y3_N2; Fanout = 2; REG Node = 'fenpin:inst11\|clk1'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.274 ns" { clk0 fenpin:inst11|clk1 } "NODE_NAME" } } { "fenpin.v" "" { Text "F:/altera/可调三角波/fenpin.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clk0 fenpin:inst11|clk1 } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { clk0 clk0~out0 fenpin:inst11|clk1 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 2.743 ns - Longest register " "Info: - Longest clock path from clock \"clk0\" to source register is 2.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk0 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'clk0'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 248 -768 -600 264 "clk0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.711 ns) 2.743 ns fenpin:inst11\|clk1 2 REG LC_X26_Y3_N2 2 " "Info: 2: + IC(0.563 ns) + CELL(0.711 ns) = 2.743 ns; Loc. = LC_X26_Y3_N2; Fanout = 2; REG Node = 'fenpin:inst11\|clk1'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.274 ns" { clk0 fenpin:inst11|clk1 } "NODE_NAME" } } { "fenpin.v" "" { Text "F:/altera/可调三角波/fenpin.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.48 % ) " "Info: Total cell delay = 2.180 ns ( 79.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.52 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clk0 fenpin:inst11|clk1 } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { clk0 clk0~out0 fenpin:inst11|clk1 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clk0 fenpin:inst11|clk1 } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { clk0 clk0~out0 fenpin:inst11|clk1 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clk0 fenpin:inst11|clk1 } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { clk0 clk0~out0 fenpin:inst11|clk1 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "fenpin.v" "" { Text "F:/altera/可调三角波/fenpin.v" 3 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "fenpin.v" "" { Text "F:/altera/可调三角波/fenpin.v" 3 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clk0 fenpin:inst11|clk1 } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { clk0 clk0~out0 fenpin:inst11|clk1 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clk0 fenpin:inst11|clk1 } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { clk0 clk0~out0 fenpin:inst11|clk1 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.014 ns - Longest register register " "Info: - Longest register to register delay is 1.014 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fenpin:inst11\|clk1 1 REG LC_X26_Y3_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y3_N2; Fanout = 2; REG Node = 'fenpin:inst11\|clk1'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fenpin:inst11|clk1 } "NODE_NAME" } } { "fenpin.v" "" { Text "F:/altera/可调三角波/fenpin.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.536 ns) + CELL(0.478 ns) 1.014 ns fenpin:inst11\|clk1 2 REG LC_X26_Y3_N2 2 " "Info: 2: + IC(0.536 ns) + CELL(0.478 ns) = 1.014 ns; Loc. = LC_X26_Y3_N2; Fanout = 2; REG Node = 'fenpin:inst11\|clk1'" {  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.014 ns" { fenpin:inst11|clk1 fenpin:inst11|clk1 } "NODE_NAME" } } { "fenpin.v" "" { Text "F:/altera/可调三角波/fenpin.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns ( 47.14 % ) " "Info: Total cell delay = 0.478 ns ( 47.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.536 ns ( 52.86 % ) " "Info: Total interconnect delay = 0.536 ns ( 52.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.014 ns" { fenpin:inst11|clk1 fenpin:inst11|clk1 } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "1.014 ns" { fenpin:inst11|clk1 fenpin:inst11|clk1 } { 0.000ns 0.536ns } { 0.000ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clk0 fenpin:inst11|clk1 } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { clk0 clk0~out0 fenpin:inst11|clk1 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.743 ns" { clk0 fenpin:inst11|clk1 } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.743 ns" { clk0 clk0~out0 fenpin:inst11|clk1 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.014 ns" { fenpin:inst11|clk1 fenpin:inst11|clk1 } "NODE_NAME" } } { "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus60/win/Technology_Viewer.qrui" "1.014 ns" { fenpin:inst11|clk1 fenpin:inst11|clk1 } { 0.000ns 0.536ns } { 0.000ns 0.478ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}