trian.tan.qmsg

FPGA编写的三角波发生器

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "cs " "Info: Assuming node \"cs\" is an undefined clock" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 320 -208 -40 336 "cs" "" } } } } { "e:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cs" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "datinclk " "Info: Assuming node \"datinclk\" is an undefined clock" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 392 -248 -80 408 "datinclk" "" } } } } { "e:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "datinclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "addrclk " "Info: Assuming node \"addrclk\" is an undefined clock" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 456 -240 -72 472 "addrclk" "" } } } } { "e:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "addrclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "fswclk " "Info: Assuming node \"fswclk\" is an undefined clock" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 616 -168 0 632 "fswclk" "" } } } } { "e:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fswclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "inst19~15 " "Info: Detected gated clock \"inst19~15\" as buffer" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 744 432 496 792 "inst19" "" } } } } { "e:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "inst19~15" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst10~11 " "Info: Detected gated clock \"inst10~11\" as buffer" {  } { { "trian.bdf" "" { Schematic "F:/altera/可调三角波/trian.bdf" { { 280 712 776 328 "inst10" "" } } } } { "e:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "inst10~11" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}