trian.hier_info

FPGA编写的三角波发生器

addrs1[4] => addr0~5.DATAB
addrs1[5] => addr0~4.DATAB
addrs1[6] => addr0~3.DATAB
addrs1[7] => addr0~2.DATAB
addrs1[8] => addr0~1.DATAB
addrs1[9] => addr0~0.DATAB
addrs2[0] => addr0~9.DATAA
addrs2[1] => addr0~8.DATAA
addrs2[2] => addr0~7.DATAA
addrs2[3] => addr0~6.DATAA
addrs2[4] => addr0~5.DATAA
addrs2[5] => addr0~4.DATAA
addrs2[6] => addr0~3.DATAA
addrs2[7] => addr0~2.DATAA
addrs2[8] => addr0~1.DATAA
addrs2[9] => addr0~0.DATAA


|trian|bianpin:inst3
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[4] <= counter[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[5] <= counter[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[6] <= counter[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[7] <= counter[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[8] <= counter[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[9] <= counter[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[10] <= counter[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[11] <= counter[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[12] <= counter[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[13] <= counter[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[14] <= counter[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[15] <= counter[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[16] <= counter[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[17] <= counter[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[18] <= counter[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[19] <= counter[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[20] <= counter[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[21] <= counter[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[22] <= counter[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[23] <= counter[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[24] <= counter[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[25] <= counter[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[26] <= counter[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[27] <= counter[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[28] <= counter[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[29] <= counter[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk => counter[28]~reg0.CLK
clk => counter[27]~reg0.CLK
clk => counter[26]~reg0.CLK
clk => counter[25]~reg0.CLK
clk => counter[24]~reg0.CLK
clk => counter[23]~reg0.CLK
clk => counter[22]~reg0.CLK
clk => counter[21]~reg0.CLK
clk => counter[20]~reg0.CLK
clk => counter[19]~reg0.CLK
clk => counter[18]~reg0.CLK
clk => counter[17]~reg0.CLK
clk => counter[16]~reg0.CLK
clk => counter[15]~reg0.CLK
clk => counter[14]~reg0.CLK
clk => counter[13]~reg0.CLK
clk => counter[12]~reg0.CLK
clk => counter[11]~reg0.CLK
clk => counter[10]~reg0.CLK
clk => counter[9]~reg0.CLK
clk => counter[8]~reg0.CLK
clk => counter[7]~reg0.CLK
clk => counter[6]~reg0.CLK
clk => counter[5]~reg0.CLK
clk => counter[4]~reg0.CLK
clk => counter[3]~reg0.CLK
clk => counter[2]~reg0.CLK
clk => counter[1]~reg0.CLK
clk => counter[0]~reg0.CLK
clk => counter[29]~reg0.CLK
fsw[0] => Add0.IN60
fsw[1] => Add0.IN59
fsw[2] => Add0.IN58
fsw[3] => Add0.IN57
fsw[4] => Add0.IN56
fsw[5] => Add0.IN55
fsw[6] => Add0.IN54
fsw[7] => Add0.IN53
fsw[8] => Add0.IN52
fsw[9] => Add0.IN51
fsw[10] => Add0.IN50
fsw[11] => Add0.IN49
fsw[12] => Add0.IN48
fsw[13] => Add0.IN47
fsw[14] => Add0.IN46
fsw[15] => Add0.IN45
fsw[16] => Add0.IN44
fsw[17] => Add0.IN43
fsw[18] => Add0.IN42
fsw[19] => Add0.IN41
fsw[20] => Add0.IN40
fsw[21] => Add0.IN39
fsw[22] => Add0.IN38
fsw[23] => Add0.IN37
fsw[24] => Add0.IN36
fsw[25] => Add0.IN35
fsw[26] => Add0.IN34
fsw[27] => Add0.IN33


|trian|fsw:inst16
clock => clock~0.IN1
shiftin => shiftin~0.IN1
q[0] <= lpm_shiftreg:lpm_shiftreg_component.q
q[1] <= lpm_shiftreg:lpm_shiftreg_component.q
q[2] <= lpm_shiftreg:lpm_shiftreg_component.q
q[3] <= lpm_shiftreg:lpm_shiftreg_component.q
q[4] <= lpm_shiftreg:lpm_shiftreg_component.q
q[5] <= lpm_shiftreg:lpm_shiftreg_component.q
q[6] <= lpm_shiftreg:lpm_shiftreg_component.q
q[7] <= lpm_shiftreg:lpm_shiftreg_component.q
q[8] <= lpm_shiftreg:lpm_shiftreg_component.q
q[9] <= lpm_shiftreg:lpm_shiftreg_component.q
q[10] <= lpm_shiftreg:lpm_shiftreg_component.q
q[11] <= lpm_shiftreg:lpm_shiftreg_component.q
q[12] <= lpm_shiftreg:lpm_shiftreg_component.q
q[13] <= lpm_shiftreg:lpm_shiftreg_component.q
q[14] <= lpm_shiftreg:lpm_shiftreg_component.q
q[15] <= lpm_shiftreg:lpm_shiftreg_component.q
q[16] <= lpm_shiftreg:lpm_shiftreg_component.q
q[17] <= lpm_shiftreg:lpm_shiftreg_component.q
q[18] <= lpm_shiftreg:lpm_shiftreg_component.q
q[19] <= lpm_shiftreg:lpm_shiftreg_component.q
q[20] <= lpm_shiftreg:lpm_shiftreg_component.q
q[21] <= lpm_shiftreg:lpm_shiftreg_component.q
q[22] <= lpm_shiftreg:lpm_shiftreg_component.q
q[23] <= lpm_shiftreg:lpm_shiftreg_component.q
q[24] <= lpm_shiftreg:lpm_shiftreg_component.q
q[25] <= lpm_shiftreg:lpm_shiftreg_component.q
q[26] <= lpm_shiftreg:lpm_shiftreg_component.q
q[27] <= lpm_shiftreg:lpm_shiftreg_component.q


|trian|fsw:inst16|lpm_shiftreg:lpm_shiftreg_component
clock => dffs[27].CLK
clock => dffs[26].CLK
clock => dffs[25].CLK
clock => dffs[24].CLK
clock => dffs[23].CLK
clock => dffs[22].CLK
clock => dffs[21].CLK
clock => dffs[20].CLK
clock => dffs[19].CLK
clock => dffs[18].CLK
clock => dffs[17].CLK
clock => dffs[16].CLK
clock => dffs[15].CLK
clock => dffs[14].CLK
clock => dffs[13].CLK
clock => dffs[12].CLK
clock => dffs[11].CLK
clock => dffs[10].CLK
clock => dffs[9].CLK
clock => dffs[8].CLK
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[27].ENA
enable => dffs[26].ENA
enable => dffs[25].ENA
enable => dffs[24].ENA
enable => dffs[23].ENA
enable => dffs[22].ENA
enable => dffs[21].ENA
enable => dffs[20].ENA
enable => dffs[19].ENA
enable => dffs[18].ENA
enable => dffs[17].ENA
enable => dffs[16].ENA
enable => dffs[15].ENA
enable => dffs[14].ENA
enable => dffs[13].ENA
enable => dffs[12].ENA
enable => dffs[11].ENA
enable => dffs[10].ENA
enable => dffs[9].ENA
enable => dffs[8].ENA
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffs[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffs[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= dffs[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= dffs[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= dffs[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= dffs[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= dffs[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= dffs[15].DB_MAX_OUTPUT_PORT_TYPE
q[16] <= dffs[16].DB_MAX_OUTPUT_PORT_TYPE
q[17] <= dffs[17].DB_MAX_OUTPUT_PORT_TYPE
q[18] <= dffs[18].DB_MAX_OUTPUT_PORT_TYPE
q[19] <= dffs[19].DB_MAX_OUTPUT_PORT_TYPE
q[20] <= dffs[20].DB_MAX_OUTPUT_PORT_TYPE
q[21] <= dffs[21].DB_MAX_OUTPUT_PORT_TYPE
q[22] <= dffs[22].DB_MAX_OUTPUT_PORT_TYPE
q[23] <= dffs[23].DB_MAX_OUTPUT_PORT_TYPE
q[24] <= dffs[24].DB_MAX_OUTPUT_PORT_TYPE
q[25] <= dffs[25].DB_MAX_OUTPUT_PORT_TYPE
q[26] <= dffs[26].DB_MAX_OUTPUT_PORT_TYPE
q[27] <= dffs[27].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|trian|dat:inst18
clock => clock~0.IN1
shiftin => shiftin~0.IN1
q[0] <= lpm_shiftreg:lpm_shiftreg_component.q
q[1] <= lpm_shiftreg:lpm_shiftreg_component.q
q[2] <= lpm_shiftreg:lpm_shiftreg_component.q
q[3] <= lpm_shiftreg:lpm_shiftreg_component.q
q[4] <= lpm_shiftreg:lpm_shiftreg_component.q
q[5] <= lpm_shiftreg:lpm_shiftreg_component.q
q[6] <= lpm_shiftreg:lpm_shiftreg_component.q
q[7] <= lpm_shiftreg:lpm_shiftreg_component.q
q[8] <= lpm_shiftreg:lpm_shiftreg_component.q
q[9] <= lpm_shiftreg:lpm_shiftreg_component.q


|trian|dat:inst18|lpm_shiftreg:lpm_shiftreg_component
clock => dffs[9].CLK
clock => dffs[8].CLK
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[9].ENA
enable => dffs[8].ENA
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffs[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffs[9].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE


|trian|datin:inst1
clock => clock~0.IN1
shiftin => shiftin~0.IN1
q[0] <= lpm_shiftreg:lpm_shiftreg_component.q
q[1] <= lpm_shiftreg:lpm_shiftreg_component.q
q[2] <= lpm_shiftreg:lpm_shiftreg_component.q
q[3] <= lpm_shiftreg:lpm_shiftreg_component.q
q[4] <= lpm_shiftreg:lpm_shiftreg_component.q
q[5] <= lpm_shiftreg:lpm_shiftreg_component.q
q[6] <= lpm_shiftreg:lpm_shiftreg_component.q
q[7] <= lpm_shiftreg:lpm_shiftreg_component.q


|trian|datin:inst1|lpm_shiftreg:lpm_shiftreg_component
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[7].ENA
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= shiftout~0.DB_MAX_OUTPUT_PORT_TYPE