trian.hier_info

FPGA编写的三角波发生器

|trian
p33 <= fenpin:inst11.p33
clk0 => fenpin:inst11.clk0
clk0 => pll:inst5.inclk0
p35 <= fenpin:inst11.p35
swt3 <= fenpin:inst11.swt3
swt2 <= fenpin:inst11.swt2
tcs <= fenpin:inst11.tcs
treg <= fenpin:inst11.treg
we <= sinwave:inst4.clkout
cs => inst9.IN0
cs => inst7.IN1
cs => chooseaddr:inst2.en
cs => inst19.IN0
senddatclk => inst8.IN1
clk0out <= fenpin:inst11.clk1
datout[0] <= wave:inst.q[0]
datout[1] <= wave:inst.q[1]
datout[2] <= wave:inst.q[2]
datout[3] <= wave:inst.q[3]
datout[4] <= wave:inst.q[4]
datout[5] <= wave:inst.q[5]
datout[6] <= wave:inst.q[6]
datout[7] <= wave:inst.q[7]
wren => wave:inst.wren
fswclk => fsw:inst16.clock
fswdat => fsw:inst16.shiftin
addrclk => dat:inst18.clock
addrdat => dat:inst18.shiftin
datinclk => datin:inst1.clock
datin => datin:inst1.shiftin


|trian|fenpin:inst11
tcs <= <GND>
treg <= <GND>
clk1 <= clk1~reg0.DB_MAX_OUTPUT_PORT_TYPE
p33 <= <GND>
p35 <= <GND>
swt3 <= <VCC>
swt2 <= <VCC>
clk0 => clk1~reg0.CLK


|trian|sinwave:inst4
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE
clkin => temp[9].CLK
clkin => temp[8].CLK
clkin => temp[7].CLK
clkin => temp[6].CLK
clkin => temp[5].CLK
clkin => temp[4].CLK
clkin => temp[3].CLK
clkin => temp[2].CLK
clkin => temp[1].CLK
clkin => temp[0].CLK
clkin => clkout~reg0.CLK
clkin => temp[10].CLK


|trian|pll:inst5
inclk0 => sub_wire3[0].IN1
c0 <= altpll:altpll_component.clk


|trian|pll:inst5|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => pll.ENA2
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= <UNC>
clk[2] <= pll.CLK2
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE


|trian|wave:inst
address[0] => address[0]~9.IN1
address[1] => address[1]~8.IN1
address[2] => address[2]~7.IN1
address[3] => address[3]~6.IN1
address[4] => address[4]~5.IN1
address[5] => address[5]~4.IN1
address[6] => address[6]~3.IN1
address[7] => address[7]~2.IN1
address[8] => address[8]~1.IN1
address[9] => address[9]~0.IN1
clock => clock~0.IN1
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
wren => wren~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|trian|wave:inst|altsyncram:altsyncram_component
wren_a => altsyncram_aaa1:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_aaa1:auto_generated.data_a[0]
data_a[1] => altsyncram_aaa1:auto_generated.data_a[1]
data_a[2] => altsyncram_aaa1:auto_generated.data_a[2]
data_a[3] => altsyncram_aaa1:auto_generated.data_a[3]
data_a[4] => altsyncram_aaa1:auto_generated.data_a[4]
data_a[5] => altsyncram_aaa1:auto_generated.data_a[5]
data_a[6] => altsyncram_aaa1:auto_generated.data_a[6]
data_a[7] => altsyncram_aaa1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_aaa1:auto_generated.address_a[0]
address_a[1] => altsyncram_aaa1:auto_generated.address_a[1]
address_a[2] => altsyncram_aaa1:auto_generated.address_a[2]
address_a[3] => altsyncram_aaa1:auto_generated.address_a[3]
address_a[4] => altsyncram_aaa1:auto_generated.address_a[4]
address_a[5] => altsyncram_aaa1:auto_generated.address_a[5]
address_a[6] => altsyncram_aaa1:auto_generated.address_a[6]
address_a[7] => altsyncram_aaa1:auto_generated.address_a[7]
address_a[8] => altsyncram_aaa1:auto_generated.address_a[8]
address_a[9] => altsyncram_aaa1:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_aaa1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_aaa1:auto_generated.q_a[0]
q_a[1] <= altsyncram_aaa1:auto_generated.q_a[1]
q_a[2] <= altsyncram_aaa1:auto_generated.q_a[2]
q_a[3] <= altsyncram_aaa1:auto_generated.q_a[3]
q_a[4] <= altsyncram_aaa1:auto_generated.q_a[4]
q_a[5] <= altsyncram_aaa1:auto_generated.q_a[5]
q_a[6] <= altsyncram_aaa1:auto_generated.q_a[6]
q_a[7] <= altsyncram_aaa1:auto_generated.q_a[7]
q_b[0] <= <GND>


|trian|wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE


|trian|chooseaddr:inst2
clk => addr0[8]~reg0.CLK
clk => addr0[7]~reg0.CLK
clk => addr0[6]~reg0.CLK
clk => addr0[5]~reg0.CLK
clk => addr0[4]~reg0.CLK
clk => addr0[3]~reg0.CLK
clk => addr0[2]~reg0.CLK
clk => addr0[1]~reg0.CLK
clk => addr0[0]~reg0.CLK
clk => addr0[9]~reg0.CLK
addr0[0] <= addr0[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr0[1] <= addr0[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr0[2] <= addr0[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr0[3] <= addr0[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr0[4] <= addr0[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr0[5] <= addr0[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr0[6] <= addr0[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr0[7] <= addr0[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr0[8] <= addr0[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr0[9] <= addr0[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
en => Decoder0.IN0
addrs1[0] => addr0~9.DATAB
addrs1[1] => addr0~8.DATAB
addrs1[2] => addr0~7.DATAB
addrs1[3] => addr0~6.DATAB