trian.qsf

FPGA编写的三角波发生器

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		trian_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C3T144C8
set_global_assignment -name TOP_LEVEL_ENTITY trian
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:06:11  AUGUST 14, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_timing_analysis
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_timing_analysis
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_location_assignment PIN_98 -to addrclk
set_location_assignment PIN_100 -to addrdat
set_location_assignment PIN_104 -to fswclk
set_location_assignment PIN_106 -to fswdat
set_location_assignment PIN_17 -to clk0
set_location_assignment PIN_108 -to cs
set_location_assignment PIN_110 -to wren
set_location_assignment PIN_72 -to datout[7]
set_location_assignment PIN_74 -to datout[6]
set_location_assignment PIN_76 -to datout[5]
set_location_assignment PIN_78 -to datout[4]
set_location_assignment PIN_82 -to datout[3]
set_location_assignment PIN_84 -to datout[2]
set_location_assignment PIN_91 -to datout[1]
set_location_assignment PIN_96 -to datout[0]
set_location_assignment PIN_33 -to p33
set_location_assignment PIN_35 -to p35
set_location_assignment PIN_112 -to senddatclk
set_location_assignment PIN_48 -to swt2
set_location_assignment PIN_49 -to swt3
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_location_assignment PIN_99 -to datin
set_location_assignment PIN_97 -to datinclk
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
set_location_assignment PIN_73 -to we
set_location_assignment PIN_71 -to tcs
set_location_assignment PIN_75 -to treg
set_location_assignment PIN_77 -to clk0out
set_global_assignment -name VERILOG_FILE pll.v
set_global_assignment -name VERILOG_FILE datin.v
set_global_assignment -name VERILOG_FILE wave.v
set_global_assignment -name VERILOG_FILE dat.v
set_global_assignment -name VERILOG_FILE fsw.v
set_global_assignment -name VERILOG_FILE chooseaddr.v
set_global_assignment -name VERILOG_FILE bianpin.v
set_global_assignment -name VERILOG_FILE fenpin.v
set_global_assignment -name BDF_FILE trian.bdf
set_global_assignment -name VERILOG_FILE sinwave.v