trian.vho

FPGA编写的三角波发生器

--	oe_register_mode => "none",
--	oe_sync_reset => "none",
--	operation_mode => "input",
--	output_async_reset => "none",
--	output_power_up => "low",
--	output_register_mode => "none",
--	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => \addrclk~I_modesel\,
	combout => \addrclk~combout\,
	padio => ww_addrclk);

-- atom is at PIN_104
\fswclk~I\ : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	input_async_reset => "none",
--	input_power_up => "low",
--	input_register_mode => "none",
--	input_sync_reset => "none",
--	oe_async_reset => "none",
--	oe_power_up => "low",
--	oe_register_mode => "none",
--	oe_sync_reset => "none",
--	operation_mode => "input",
--	output_async_reset => "none",
--	output_power_up => "low",
--	output_register_mode => "none",
--	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => \fswclk~I_modesel\,
	combout => \fswclk~combout\,
	padio => ww_fswclk);

-- atom is at PIN_112
\senddatclk~I\ : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	input_async_reset => "none",
--	input_power_up => "low",
--	input_register_mode => "none",
--	input_sync_reset => "none",
--	oe_async_reset => "none",
--	oe_power_up => "low",
--	oe_register_mode => "none",
--	oe_sync_reset => "none",
--	operation_mode => "input",
--	output_async_reset => "none",
--	output_power_up => "low",
--	output_register_mode => "none",
--	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => \senddatclk~I_modesel\,
	combout => \senddatclk~combout\,
	padio => ww_senddatclk);

-- atom is at PIN_108
\cs~I\ : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	input_async_reset => "none",
--	input_power_up => "low",
--	input_register_mode => "none",
--	input_sync_reset => "none",
--	oe_async_reset => "none",
--	oe_power_up => "low",
--	oe_register_mode => "none",
--	oe_sync_reset => "none",
--	operation_mode => "input",
--	output_async_reset => "none",
--	output_power_up => "low",
--	output_register_mode => "none",
--	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => \cs~I_modesel\,
	combout => \cs~combout\,
	padio => ww_cs);

-- atom is at PIN_17
\clk0~I\ : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	input_async_reset => "none",
--	input_power_up => "low",
--	input_register_mode => "none",
--	input_sync_reset => "none",
--	oe_async_reset => "none",
--	oe_power_up => "low",
--	oe_register_mode => "none",
--	oe_sync_reset => "none",
--	operation_mode => "input",
--	output_async_reset => "none",
--	output_power_up => "low",
--	output_register_mode => "none",
--	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => \clk0~I_modesel\,
	combout => \clk0~combout\,
	padio => ww_clk0);

-- atom is at PLL_1
\inst5|altpll_component|_clk0~I\ : cyclone_pll
-- pragma translate_off
-- GENERIC MAP (
--	bandwidth => 2591093,
--	bandwidth_type => "auto",
--	charge_pump_current => 40,
--	clk0_counter => "g1",
--	clk0_divide_by => 1,
--	clk0_duty_cycle => 50,
--	clk0_multiply_by => 16,
--	clk0_phase_shift => "0",
--	clk0_time_delay => "0",
--	clk1_divide_by => 1,
--	clk1_duty_cycle => 50,
--	clk1_multiply_by => 1,
--	clk1_phase_shift => "0",
--	clk1_time_delay => "0",
--	clk2_divide_by => 1,
--	clk2_duty_cycle => 50,
--	clk2_multiply_by => 1,
--	clk2_phase_shift => "0",
--	clk2_time_delay => "0",
--	clk3_divide_by => 1,
--	clk3_duty_cycle => 50,
--	clk3_multiply_by => 1,
--	clk3_phase_shift => "0",
--	clk3_time_delay => "0",
--	clk4_divide_by => 1,
--	clk4_duty_cycle => 50,
--	clk4_multiply_by => 1,
--	clk4_phase_shift => "0",
--	clk4_time_delay => "0",
--	clk5_divide_by => 1,
--	clk5_duty_cycle => 50,
--	clk5_multiply_by => 1,
--	clk5_phase_shift => "0",
--	clk5_time_delay => "0",
--	compensate_clock => "clk0",
--	down_spread => "0 %",
--	e0_mode => "bypass",
--	e0_ph => 0,
--	e0_time_delay => 0,
--	e1_mode => "bypass",
--	e1_ph => 0,
--	e1_time_delay => 0,
--	e2_mode => "bypass",
--	e2_ph => 0,
--	e2_time_delay => 0,
--	e3_mode => "bypass",
--	e3_ph => 0,
--	e3_time_delay => 0,
--	enable_switch_over_counter => "off",
--	extclk0_divide_by => 1,
--	extclk0_duty_cycle => 50,
--	extclk0_multiply_by => 1,
--	extclk0_phase_shift => "0",
--	extclk0_time_delay => "0",
--	extclk1_divide_by => 1,
--	extclk1_duty_cycle => 50,
--	extclk1_multiply_by => 1,
--	extclk1_phase_shift => "0",
--	extclk1_time_delay => "0",
--	extclk2_divide_by => 1,
--	extclk2_duty_cycle => 50,
--	extclk2_multiply_by => 1,
--	extclk2_phase_shift => "0",
--	extclk2_time_delay => "0",
--	extclk3_divide_by => 1,
--	extclk3_duty_cycle => 50,
--	extclk3_multiply_by => 1,
--	extclk3_phase_shift => "0",
--	extclk3_time_delay => "0",
--	g0_mode => "bypass",
--	g0_ph => 0,
--	g0_time_delay => 0,
--	g1_high => 1,
--	g1_initial => 1,
--	g1_low => 1,
--	g1_mode => "even",
--	g1_ph => 0,
--	g1_time_delay => 0,
--	g2_mode => "bypass",
--	g2_ph => 0,
--	g2_time_delay => 0,
--	g3_mode => "bypass",
--	g3_ph => 0,
--	g3_time_delay => 0,
--	gate_lock_counter => 0,
--	gate_lock_signal => "no",
--	inclk0_input_frequency => 62500,
--	inclk1_input_frequency => 62500,
--	invalid_lock_multiplier => 5,
--	l0_high => 1,
--	l0_initial => 1,
--	l0_low => 1,
--	l0_mode => "even",
--	l0_ph => 0,
--	l0_time_delay => 0,
--	l1_mode => "bypass",
--	l1_ph => 0,
--	l1_time_delay => 0,
--	loop_filter_c => 10,
--	loop_filter_r => "1.021000",
--	m => 32,
--	m2 => 1,
--	m_initial => 1,
--	m_ph => 0,
--	m_time_delay => 0,
--	n => 1,
--	n2 => 1,
--	n_time_delay => 0,
--	operation_mode => "normal",
--	pfd_max => 66666,
--	pfd_min => 5000,
--	pll_compensation_delay => 5148,
--	pll_type => "auto",
--	primary_clock => "inclk0",
--	qualify_conf_done => "off",
--	simulation_type => "timing",
--	skip_vco => "off",
--	spread_frequency => 0,
--	switch_over_counter => 1,
--	switch_over_on_gated_lock => "off",
--	switch_over_on_lossclk => "off",
--	valid_lock_multiplier => 1,
--	vco_center => 1250,
--	vco_max => 2037,
--	vco_min => 1000)
-- pragma translate_on
PORT MAP (