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📄 trian.vho

📁 FPGA编写的三角波发生器
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\inst3|counter[13]~I_pathsel\ <= "01110010011";
\inst3|counter[14]~I_modesel\ <= "1100010010110";
\inst3|counter[14]~I_pathsel\ <= "01110010011";
\inst3|counter[15]~I_modesel\ <= "1100010010110";
\inst3|counter[15]~I_pathsel\ <= "01110010011";
\inst3|counter[16]~I_modesel\ <= "1100010010110";
\inst3|counter[16]~I_pathsel\ <= "01110010011";
\inst3|counter[17]~I_modesel\ <= "1100010010110";
\inst3|counter[17]~I_pathsel\ <= "01110010011";
\inst3|counter[18]~I_modesel\ <= "1100010010110";
\inst3|counter[18]~I_pathsel\ <= "01110010011";
\inst3|counter[19]~I_modesel\ <= "1100010010110";
\inst3|counter[19]~I_pathsel\ <= "01110010011";
\inst3|counter[20]~I_modesel\ <= "1100010010110";
\inst3|counter[20]~I_pathsel\ <= "01110010011";
\inst2|addr0[0]~I_modesel\ <= "1100001010101";
\inst2|addr0[0]~I_pathsel\ <= "00000001101";
\inst18|lpm_shiftreg_component|dffs[1]~I_modesel\ <= "0100001011001";
\inst18|lpm_shiftreg_component|dffs[1]~I_pathsel\ <= "00000000000";
\inst16|lpm_shiftreg_component|dffs[21]~I_modesel\ <= "1100001010101";
\inst16|lpm_shiftreg_component|dffs[21]~I_pathsel\ <= "00000001000";
\inst3|counter[21]~I_modesel\ <= "1100010010110";
\inst3|counter[21]~I_pathsel\ <= "01110010011";
\inst2|addr0[1]~I_modesel\ <= "1100001010101";
\inst2|addr0[1]~I_pathsel\ <= "00000000111";
\inst18|lpm_shiftreg_component|dffs[2]~I_modesel\ <= "0100001011001";
\inst18|lpm_shiftreg_component|dffs[2]~I_pathsel\ <= "00000000000";
\inst16|lpm_shiftreg_component|dffs[22]~I_modesel\ <= "0100001011001";
\inst16|lpm_shiftreg_component|dffs[22]~I_pathsel\ <= "00000000000";
\inst3|counter[22]~I_modesel\ <= "1100010010110";
\inst3|counter[22]~I_pathsel\ <= "01110010011";
\inst2|addr0[2]~I_modesel\ <= "1100001010101";
\inst2|addr0[2]~I_pathsel\ <= "00000000111";
\inst18|lpm_shiftreg_component|dffs[3]~I_modesel\ <= "0100001011001";
\inst18|lpm_shiftreg_component|dffs[3]~I_pathsel\ <= "00000000000";
\inst16|lpm_shiftreg_component|dffs[23]~I_modesel\ <= "1100001010101";
\inst16|lpm_shiftreg_component|dffs[23]~I_pathsel\ <= "00000001000";
\inst3|counter[23]~I_modesel\ <= "1100010010110";
\inst3|counter[23]~I_pathsel\ <= "01110010011";
\inst2|addr0[3]~I_modesel\ <= "1100001010101";
\inst2|addr0[3]~I_pathsel\ <= "00000000111";
\inst16|lpm_shiftreg_component|dffs[24]~I_modesel\ <= "0100001011001";
\inst16|lpm_shiftreg_component|dffs[24]~I_pathsel\ <= "00000000000";
\inst3|counter[24]~I_modesel\ <= "1100010010110";
\inst3|counter[24]~I_pathsel\ <= "01110010011";
\inst18|lpm_shiftreg_component|dffs[4]~I_modesel\ <= "1100001010101";
\inst18|lpm_shiftreg_component|dffs[4]~I_pathsel\ <= "00000001000";
\inst2|addr0[4]~I_modesel\ <= "1100001010101";
\inst2|addr0[4]~I_pathsel\ <= "00000000111";
\inst18|lpm_shiftreg_component|dffs[5]~I_modesel\ <= "0100001011001";
\inst18|lpm_shiftreg_component|dffs[5]~I_pathsel\ <= "00000000000";
\inst16|lpm_shiftreg_component|dffs[25]~I_modesel\ <= "0100001011001";
\inst16|lpm_shiftreg_component|dffs[25]~I_pathsel\ <= "00000000000";
\inst3|counter[25]~I_modesel\ <= "1100010010110";
\inst3|counter[25]~I_pathsel\ <= "01110010011";
\inst2|addr0[5]~I_modesel\ <= "1100001010101";
\inst2|addr0[5]~I_pathsel\ <= "00000001110";
\inst16|lpm_shiftreg_component|dffs[26]~I_modesel\ <= "0100001011001";
\inst16|lpm_shiftreg_component|dffs[26]~I_pathsel\ <= "00000000000";
\inst3|counter[26]~I_modesel\ <= "1100010010110";
\inst3|counter[26]~I_pathsel\ <= "01110010011";
\inst18|lpm_shiftreg_component|dffs[6]~I_modesel\ <= "0100001011001";
\inst18|lpm_shiftreg_component|dffs[6]~I_pathsel\ <= "00000000000";
\inst2|addr0[6]~I_modesel\ <= "1100001010101";
\inst2|addr0[6]~I_pathsel\ <= "00000000111";
\inst16|lpm_shiftreg_component|dffs[27]~I_modesel\ <= "0100001011001";
\inst16|lpm_shiftreg_component|dffs[27]~I_pathsel\ <= "00000000000";
\inst3|counter[27]~I_modesel\ <= "1100010010110";
\inst3|counter[27]~I_pathsel\ <= "01110010011";
\inst18|lpm_shiftreg_component|dffs[7]~I_modesel\ <= "0100001011001";
\inst18|lpm_shiftreg_component|dffs[7]~I_pathsel\ <= "00000000000";
\inst2|addr0[7]~I_modesel\ <= "1100001010101";
\inst2|addr0[7]~I_pathsel\ <= "00000000111";
\inst3|counter[28]~I_modesel\ <= "1100010010110";
\inst3|counter[28]~I_pathsel\ <= "01100010010";
\inst18|lpm_shiftreg_component|dffs[8]~I_modesel\ <= "0100001011001";
\inst18|lpm_shiftreg_component|dffs[8]~I_pathsel\ <= "00000000000";
\inst2|addr0[8]~I_modesel\ <= "1100001010101";
\inst2|addr0[8]~I_pathsel\ <= "00000000111";
\inst3|counter[29]~I_modesel\ <= "1100010010101";
\inst3|counter[29]~I_pathsel\ <= "00000010001";
\inst18|lpm_shiftreg_component|dffs[9]~I_modesel\ <= "1100001010101";
\inst18|lpm_shiftreg_component|dffs[9]~I_pathsel\ <= "00000001000";
\inst2|addr0[9]~I_modesel\ <= "1100001010101";
\inst2|addr0[9]~I_pathsel\ <= "00000001110";
\inst|altsyncram_component|auto_generated|q_a[7]~I_modesel\ <= "00000101110000000000000000000100000000001";
\inst|altsyncram_component|auto_generated|q_a[6]~I_modesel\ <= "00000101110000000000000000000100000000001";
\p33~I_modesel\ <= "000000000000000000000000010";
\p35~I_modesel\ <= "000000000000000000000000010";
\swt3~I_modesel\ <= "000000000000000000000000010";
\swt2~I_modesel\ <= "000000000000000000000000010";
\tcs~I_modesel\ <= "000000000000000000000000010";
\treg~I_modesel\ <= "000000000000000000000000010";
\we~I_modesel\ <= "000000000000000000000000010";
\clk0out~I_modesel\ <= "000000000000000000000000010";
\datout[7]~I_modesel\ <= "000000000000000000000000010";
\datout[6]~I_modesel\ <= "000000000000000000000000010";
\datout[5]~I_modesel\ <= "000000000000000000000000010";
\datout[4]~I_modesel\ <= "000000000000000000000000010";
\datout[3]~I_modesel\ <= "000000000000000000000000010";
\datout[2]~I_modesel\ <= "000000000000000000000000010";
\datout[1]~I_modesel\ <= "000000000000000000000000010";
\datout[0]~I_modesel\ <= "000000000000000000000000010";

\inst|altsyncram_component|auto_generated|q_a[7]~I_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & \inst1|lpm_shiftreg_component|dffs[1]\ & \inst1|lpm_shiftreg_component|dffs[4]\ & 
\inst1|lpm_shiftreg_component|dffs[5]\ & \inst1|lpm_shiftreg_component|dffs[7]\);

\inst|altsyncram_component|auto_generated|q_a[7]~I_PORTAADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & \inst2|addr0[9]\ & \inst2|addr0[8]\ & \inst2|addr0[7]\ & \inst2|addr0[6]\ & \inst2|addr0[5]\ & \inst2|addr0[4]\ & \inst2|addr0[3]\ & \inst2|addr0[2]\
& \inst2|addr0[1]\ & \inst2|addr0[0]\);

\inst|altsyncram_component|auto_generated|q_a[7]_pt_buf\ : AND1
PORT MAP (
	 IN1 => \inst|altsyncram_component|auto_generated|q_a[7]~I_PORTADATAOUT_bus\(0),
	 Y => \inst|altsyncram_component|auto_generated|q_a[7]\);

\inst|altsyncram_component|auto_generated|q_a[5]_pt_buf\ : AND1
PORT MAP (
	 IN1 => \inst|altsyncram_component|auto_generated|q_a[7]~I_PORTADATAOUT_bus\(1),
	 Y => \inst|altsyncram_component|auto_generated|q_a[5]\);

\inst|altsyncram_component|auto_generated|q_a[4]_pt_buf\ : AND1
PORT MAP (
	 IN1 => \inst|altsyncram_component|auto_generated|q_a[7]~I_PORTADATAOUT_bus\(2),
	 Y => \inst|altsyncram_component|auto_generated|q_a[4]\);

\inst|altsyncram_component|auto_generated|q_a[1]_pt_buf\ : AND1
PORT MAP (
	 IN1 => \inst|altsyncram_component|auto_generated|q_a[7]~I_PORTADATAOUT_bus\(3),
	 Y => \inst|altsyncram_component|auto_generated|q_a[1]\);


\inst|altsyncram_component|auto_generated|q_a[6]~I_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & \inst1|lpm_shiftreg_component|dffs[0]\ & \inst1|lpm_shiftreg_component|dffs[2]\ & 
\inst1|lpm_shiftreg_component|dffs[3]\ & \inst1|lpm_shiftreg_component|dffs[6]\);

\inst|altsyncram_component|auto_generated|q_a[6]~I_PORTAADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & \inst2|addr0[9]\ & \inst2|addr0[8]\ & \inst2|addr0[7]\ & \inst2|addr0[6]\ & \inst2|addr0[5]\ & \inst2|addr0[4]\ & \inst2|addr0[3]\ & \inst2|addr0[2]\
& \inst2|addr0[1]\ & \inst2|addr0[0]\);

\inst|altsyncram_component|auto_generated|q_a[6]_pt_buf\ : AND1
PORT MAP (
	 IN1 => \inst|altsyncram_component|auto_generated|q_a[6]~I_PORTADATAOUT_bus\(0),
	 Y => \inst|altsyncram_component|auto_generated|q_a[6]\);

\inst|altsyncram_component|auto_generated|q_a[3]_pt_buf\ : AND1
PORT MAP (
	 IN1 => \inst|altsyncram_component|auto_generated|q_a[6]~I_PORTADATAOUT_bus\(1),
	 Y => \inst|altsyncram_component|auto_generated|q_a[3]\);

\inst|altsyncram_component|auto_generated|q_a[2]_pt_buf\ : AND1
PORT MAP (
	 IN1 => \inst|altsyncram_component|auto_generated|q_a[6]~I_PORTADATAOUT_bus\(2),
	 Y => \inst|altsyncram_component|auto_generated|q_a[2]\);

\inst|altsyncram_component|auto_generated|q_a[0]_pt_buf\ : AND1
PORT MAP (
	 IN1 => \inst|altsyncram_component|auto_generated|q_a[6]~I_PORTADATAOUT_bus\(3),
	 Y => \inst|altsyncram_component|auto_generated|q_a[0]\);


\inst5|altpll_component|_clk0~I_INCLK_bus\ <= (gnd & \clk0~combout\);

\inst5|altpll_component|_clk0~I_CLKENA_bus\ <= (gnd & gnd & gnd & gnd & gnd & vcc);

\inst5|altpll_component|_clk0_pt_buf\ : AND1
PORT MAP (
	 IN1 => \inst5|altpll_component|_clk0~I_CLK_bus\(0),
	 Y => \inst5|altpll_component|_clk0\);

\inst5|altpll_component|pll~CLK1_pt_buf\ : AND1
PORT MAP (
	 IN1 => \inst5|altpll_component|_clk0~I_CLK_bus\(1),
	 Y => \inst5|altpll_component|pll~CLK1\);

\inst5|altpll_component|_clk2_pt_buf\ : AND1
PORT MAP (
	 IN1 => \inst5|altpll_component|_clk0~I_CLK_bus\(2),
	 Y => \inst5|altpll_component|_clk2\);

\inst5|altpll_component|pll~CLK3_pt_buf\ : AND1
PORT MAP (
	 IN1 => \inst5|altpll_component|_clk0~I_CLK_bus\(3),
	 Y => \inst5|altpll_component|pll~CLK3\);

\inst5|altpll_component|pll~CLK4_pt_buf\ : AND1
PORT MAP (
	 IN1 => \inst5|altpll_component|_clk0~I_CLK_bus\(4),
	 Y => \inst5|altpll_component|pll~CLK4\);

\inst5|altpll_component|pll~CLK5_pt_buf\ : AND1
PORT MAP (
	 IN1 => \inst5|altpll_component|_clk0~I_CLK_bus\(5),
	 Y => \inst5|altpll_component|pll~CLK5\);


lcell_ff_enable_asynch_arcs : AND1
PORT MAP (
	 IN1 => GND,
	 Y => lcell_ff_enable_asynch_arcs_out);

-- atom is at PIN_97
\datinclk~I\ : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	input_async_reset => "none",
--	input_power_up => "low",
--	input_register_mode => "none",
--	input_sync_reset => "none",
--	oe_async_reset => "none",
--	oe_power_up => "low",
--	oe_register_mode => "none",
--	oe_sync_reset => "none",
--	operation_mode => "input",
--	output_async_reset => "none",
--	output_power_up => "low",
--	output_register_mode => "none",
--	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => \datinclk~I_modesel\,
	combout => \datinclk~combout\,
	padio => ww_datinclk);

-- atom is at LC_X8_Y6_N2
\inst19~15_I\ : cyclone_lcell
-- Equation(s):
-- \inst19~15\ = \cs~combout\ & GLOBAL(\inst5|altpll_component|_clk0\)

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "F000",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \inst19~15_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => VCC,
	datab => VCC,
	datac => \cs~combout\,
	datad => \inst5|altpll_component|_clk0\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \inst19~15_I_modesel\,
	combout => \inst19~15\);

-- atom is at PIN_98
\addrclk~I\ : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	input_async_reset => "none",
--	input_power_up => "low",
--	input_register_mode => "none",
--	input_sync_reset => "none",
--	oe_async_reset => "none",
--	oe_power_up => "low",
12345

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