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📁 FPGA编写的三角波发生器
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	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	aload : IN STD_LOGIC;
	sclr : IN STD_LOGIC;
	sload : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	cin0 : IN STD_LOGIC;
	cin1 : IN STD_LOGIC;
	inverta : IN STD_LOGIC;
	regcascin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	cout0 : OUT STD_LOGIC;
	cout1 : OUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
	pathsel : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
	enable_asynch_arcs : IN STD_LOGIC);
END COMPONENT;

COMPONENT cyclone_io
PORT (
	datain : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	outclk : IN STD_LOGIC;
	outclkena : IN STD_LOGIC;
	inclk : IN STD_LOGIC;
	inclkena : IN STD_LOGIC;
	areset : IN STD_LOGIC;
	sreset : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(26 DOWNTO 0));
END COMPONENT;

COMPONENT cyclone_ram_block
PORT (
	portawe : IN STD_LOGIC;
	portbrewe : IN STD_LOGIC;
	clk0 : IN STD_LOGIC;
	clk1 : IN STD_LOGIC;
	ena0 : IN STD_LOGIC;
	ena1 : IN STD_LOGIC;
	clr0 : IN STD_LOGIC;
	clr1 : IN STD_LOGIC;
	portadatain : IN STD_LOGIC_VECTOR(143 DOWNTO 0);
	portaaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	portabyteenamasks : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	portbdatain : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
	portbaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	portbbyteenamasks : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	portadataout : OUT STD_LOGIC_VECTOR(143 DOWNTO 0);
	portbdataout : OUT STD_LOGIC_VECTOR(143 DOWNTO 0);
	modesel : IN STD_LOGIC_VECTOR(40 DOWNTO 0));
END COMPONENT;

COMPONENT cyclone_pll
PORT (
	fbin : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	clkswitch : IN STD_LOGIC;
	areset : IN STD_LOGIC;
	pfdena : IN STD_LOGIC;
	scanclk : IN STD_LOGIC;
	scanaclr : IN STD_LOGIC;
	scandata : IN STD_LOGIC;
	comparator : IN STD_LOGIC;
	inclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	clkena : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
	extclkena : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	activeclock : OUT STD_LOGIC;
	clkloss : OUT STD_LOGIC;
	locked : OUT STD_LOGIC;
	scandataout : OUT STD_LOGIC;
	enable0 : OUT STD_LOGIC;
	enable1 : OUT STD_LOGIC;
	clk : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
	extclk : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	clkbad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

p33 <= ww_p33;
ww_clk0 <= clk0;
p35 <= ww_p35;
swt3 <= ww_swt3;
swt2 <= ww_swt2;
tcs <= ww_tcs;
treg <= ww_treg;
we <= ww_we;
ww_cs <= cs;
ww_senddatclk <= senddatclk;
clk0out <= ww_clk0out;
datout <= ww_datout;
ww_wren <= wren;
ww_fswclk <= fswclk;
ww_fswdat <= fswdat;
ww_addrclk <= addrclk;
ww_addrdat <= addrdat;
ww_datinclk <= datinclk;
ww_datin <= datin;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

\datinclk~I_modesel\ <= "000000000000000000000000001";
\inst19~15_I_modesel\ <= "1001001010101";
\inst19~15_I_pathsel\ <= "00000001100";
\addrclk~I_modesel\ <= "000000000000000000000000001";
\fswclk~I_modesel\ <= "000000000000000000000000001";
\senddatclk~I_modesel\ <= "000000000000000000000000001";
\cs~I_modesel\ <= "000000000000000000000000001";
\clk0~I_modesel\ <= "000000000000000000000000001";
\inst10~11_I_modesel\ <= "1001001010101";
\inst10~11_I_pathsel\ <= "00000001101";
\inst4|temp[8]~I_modesel\ <= "0100001011001";
\inst4|temp[8]~I_pathsel\ <= "00000000000";
\inst4|Add0~166_I_modesel\ <= "1001001010110";
\inst4|Add0~166_I_pathsel\ <= "00100000010";
\inst4|temp[0]~I_modesel\ <= "1100001010101";
\inst4|temp[0]~I_pathsel\ <= "00000001000";
\inst4|Add0~162_I_modesel\ <= "1001010010110";
\inst4|Add0~162_I_pathsel\ <= "01100010010";
\inst4|Add0~168_I_modesel\ <= "1001010010110";
\inst4|Add0~168_I_pathsel\ <= "01100010010";
\inst4|temp[2]~I_modesel\ <= "0100001011001";
\inst4|temp[2]~I_pathsel\ <= "00000000000";
\inst4|Add0~164_I_modesel\ <= "1001010010110";
\inst4|Add0~164_I_pathsel\ <= "01010010001";
\inst4|temp[3]~I_modesel\ <= "1100001010101";
\inst4|temp[3]~I_pathsel\ <= "00000001101";
\inst4|Add0~170_I_modesel\ <= "1001010010110";
\inst4|Add0~170_I_pathsel\ <= "01100010010";
\inst4|temp[4]~I_modesel\ <= "0100001011001";
\inst4|temp[4]~I_pathsel\ <= "00000000000";
\inst4|Add0~172_I_modesel\ <= "1001010010110";
\inst4|Add0~172_I_pathsel\ <= "01100010010";
\inst4|temp[5]~I_modesel\ <= "1100001010101";
\inst4|temp[5]~I_pathsel\ <= "00000001000";
\inst4|Add0~174_I_modesel\ <= "1001010010110";
\inst4|Add0~174_I_pathsel\ <= "01100010010";
\inst4|temp[6]~I_modesel\ <= "1100001010101";
\inst4|temp[6]~I_pathsel\ <= "00000001000";
\inst4|Add0~176_I_modesel\ <= "1001010010110";
\inst4|Add0~176_I_pathsel\ <= "01010010001";
\inst4|temp[7]~I_modesel\ <= "0100001011001";
\inst4|temp[7]~I_pathsel\ <= "00000000000";
\inst4|Add0~178_I_modesel\ <= "1001010010110";
\inst4|Add0~178_I_pathsel\ <= "01100010010";
\inst4|temp[9]~I_modesel\ <= "0100001011001";
\inst4|temp[9]~I_pathsel\ <= "00000000000";
\inst4|Add0~180_I_modesel\ <= "1001010010110";
\inst4|Add0~180_I_pathsel\ <= "01010010001";
\inst4|temp[10]~I_modesel\ <= "1100001010101";
\inst4|temp[10]~I_pathsel\ <= "00000001000";
\inst4|Add0~182_I_modesel\ <= "1001010010101";
\inst4|Add0~182_I_pathsel\ <= "00000011000";
\inst4|Equal0~141_I_modesel\ <= "1001001010101";
\inst4|Equal0~141_I_pathsel\ <= "00000001111";
\inst4|Equal0~142_I_modesel\ <= "1001001010101";
\inst4|Equal0~142_I_pathsel\ <= "00000001111";
\inst4|temp[1]~I_modesel\ <= "1100001010101";
\inst4|temp[1]~I_pathsel\ <= "00000001101";
\inst4|Equal0~140_I_modesel\ <= "1001001010101";
\inst4|Equal0~140_I_pathsel\ <= "00000001111";
\inst4|clkout~I_modesel\ <= "1100001010101";
\inst4|clkout~I_pathsel\ <= "00000001110";
\inst11|clk1~I_modesel\ <= "1100001010101";
\inst11|clk1~I_pathsel\ <= "00000000100";
\wren~I_modesel\ <= "000000000000000000000000001";
\datin~I_modesel\ <= "000000000000000000000000001";
\inst1|lpm_shiftreg_component|dffs[0]~I_modesel\ <= "0100001011001";
\inst1|lpm_shiftreg_component|dffs[0]~I_pathsel\ <= "00000000000";
\inst1|lpm_shiftreg_component|dffs[1]~I_modesel\ <= "0100001011001";
\inst1|lpm_shiftreg_component|dffs[1]~I_pathsel\ <= "00000000000";
\inst1|lpm_shiftreg_component|dffs[2]~I_modesel\ <= "1100001010101";
\inst1|lpm_shiftreg_component|dffs[2]~I_pathsel\ <= "00000001000";
\inst1|lpm_shiftreg_component|dffs[3]~I_modesel\ <= "1100001010101";
\inst1|lpm_shiftreg_component|dffs[3]~I_pathsel\ <= "00000001000";
\inst1|lpm_shiftreg_component|dffs[4]~I_modesel\ <= "0100001011001";
\inst1|lpm_shiftreg_component|dffs[4]~I_pathsel\ <= "00000000000";
\inst1|lpm_shiftreg_component|dffs[5]~I_modesel\ <= "1100001010101";
\inst1|lpm_shiftreg_component|dffs[5]~I_pathsel\ <= "00000001000";
\inst1|lpm_shiftreg_component|dffs[6]~I_modesel\ <= "0100001011001";
\inst1|lpm_shiftreg_component|dffs[6]~I_pathsel\ <= "00000000000";
\inst1|lpm_shiftreg_component|dffs[7]~I_modesel\ <= "0100001011001";
\inst1|lpm_shiftreg_component|dffs[7]~I_pathsel\ <= "00000000000";
\addrdat~I_modesel\ <= "000000000000000000000000001";
\inst18|lpm_shiftreg_component|dffs[0]~I_modesel\ <= "1100001010101";
\inst18|lpm_shiftreg_component|dffs[0]~I_pathsel\ <= "00000001000";
\fswdat~I_modesel\ <= "000000000000000000000000001";
\inst16|lpm_shiftreg_component|dffs[0]~I_modesel\ <= "1100001010101";
\inst16|lpm_shiftreg_component|dffs[0]~I_pathsel\ <= "00000001000";
\inst16|lpm_shiftreg_component|dffs[1]~I_modesel\ <= "0100001011001";
\inst16|lpm_shiftreg_component|dffs[1]~I_pathsel\ <= "00000000000";
\inst16|lpm_shiftreg_component|dffs[2]~I_modesel\ <= "1100001010101";
\inst16|lpm_shiftreg_component|dffs[2]~I_pathsel\ <= "00000001000";
\inst16|lpm_shiftreg_component|dffs[3]~I_modesel\ <= "1100001010101";
\inst16|lpm_shiftreg_component|dffs[3]~I_pathsel\ <= "00000001000";
\inst16|lpm_shiftreg_component|dffs[4]~I_modesel\ <= "0100001011001";
\inst16|lpm_shiftreg_component|dffs[4]~I_pathsel\ <= "00000000000";
\inst16|lpm_shiftreg_component|dffs[5]~I_modesel\ <= "1100001010101";
\inst16|lpm_shiftreg_component|dffs[5]~I_pathsel\ <= "00000001000";
\inst16|lpm_shiftreg_component|dffs[6]~I_modesel\ <= "0100001011001";
\inst16|lpm_shiftreg_component|dffs[6]~I_pathsel\ <= "00000000000";
\inst16|lpm_shiftreg_component|dffs[7]~I_modesel\ <= "0100001011001";
\inst16|lpm_shiftreg_component|dffs[7]~I_pathsel\ <= "00000000000";
\inst16|lpm_shiftreg_component|dffs[8]~I_modesel\ <= "0100001011001";
\inst16|lpm_shiftreg_component|dffs[8]~I_pathsel\ <= "00000000000";
\inst16|lpm_shiftreg_component|dffs[9]~I_modesel\ <= "0100001011001";
\inst16|lpm_shiftreg_component|dffs[9]~I_pathsel\ <= "00000000000";
\inst16|lpm_shiftreg_component|dffs[10]~I_modesel\ <= "1100001010101";
\inst16|lpm_shiftreg_component|dffs[10]~I_pathsel\ <= "00000001000";
\inst16|lpm_shiftreg_component|dffs[11]~I_modesel\ <= "1100001010101";
\inst16|lpm_shiftreg_component|dffs[11]~I_pathsel\ <= "00000001000";
\inst16|lpm_shiftreg_component|dffs[12]~I_modesel\ <= "0100001011001";
\inst16|lpm_shiftreg_component|dffs[12]~I_pathsel\ <= "00000000000";
\inst16|lpm_shiftreg_component|dffs[13]~I_modesel\ <= "1100001010101";
\inst16|lpm_shiftreg_component|dffs[13]~I_pathsel\ <= "00000001000";
\inst16|lpm_shiftreg_component|dffs[14]~I_modesel\ <= "1100001010101";
\inst16|lpm_shiftreg_component|dffs[14]~I_pathsel\ <= "00000001000";
\inst16|lpm_shiftreg_component|dffs[15]~I_modesel\ <= "0100001011001";
\inst16|lpm_shiftreg_component|dffs[15]~I_pathsel\ <= "00000000000";
\inst16|lpm_shiftreg_component|dffs[16]~I_modesel\ <= "0100001011001";
\inst16|lpm_shiftreg_component|dffs[16]~I_pathsel\ <= "00000000000";
\inst16|lpm_shiftreg_component|dffs[17]~I_modesel\ <= "1100001010101";
\inst16|lpm_shiftreg_component|dffs[17]~I_pathsel\ <= "00000001000";
\inst16|lpm_shiftreg_component|dffs[18]~I_modesel\ <= "0100001011001";
\inst16|lpm_shiftreg_component|dffs[18]~I_pathsel\ <= "00000000000";
\inst16|lpm_shiftreg_component|dffs[19]~I_modesel\ <= "1100001010101";
\inst16|lpm_shiftreg_component|dffs[19]~I_pathsel\ <= "00000001000";
\inst16|lpm_shiftreg_component|dffs[20]~I_modesel\ <= "1100001010101";
\inst16|lpm_shiftreg_component|dffs[20]~I_pathsel\ <= "00000001000";
\inst3|counter[0]~I_modesel\ <= "1100001010110";
\inst3|counter[0]~I_pathsel\ <= "00110000011";
\inst3|counter[1]~I_modesel\ <= "1100010010110";
\inst3|counter[1]~I_pathsel\ <= "01110010011";
\inst3|counter[2]~I_modesel\ <= "1100010010110";
\inst3|counter[2]~I_pathsel\ <= "01110010011";
\inst3|counter[3]~I_modesel\ <= "1100010010110";
\inst3|counter[3]~I_pathsel\ <= "01110010011";
\inst3|counter[4]~I_modesel\ <= "1100010010110";
\inst3|counter[4]~I_pathsel\ <= "01110010011";
\inst3|counter[5]~I_modesel\ <= "1100010010110";
\inst3|counter[5]~I_pathsel\ <= "01110010011";
\inst3|counter[6]~I_modesel\ <= "1100010010110";
\inst3|counter[6]~I_pathsel\ <= "01110010011";
\inst3|counter[7]~I_modesel\ <= "1100010010110";
\inst3|counter[7]~I_pathsel\ <= "01110010011";
\inst3|counter[8]~I_modesel\ <= "1100010010110";
\inst3|counter[8]~I_pathsel\ <= "01110010011";
\inst3|counter[9]~I_modesel\ <= "1100010010110";
\inst3|counter[9]~I_pathsel\ <= "01110010011";
\inst3|counter[10]~I_modesel\ <= "1100010010110";
\inst3|counter[10]~I_pathsel\ <= "01110010011";
\inst3|counter[11]~I_modesel\ <= "1100010010110";
\inst3|counter[11]~I_pathsel\ <= "01110010011";
\inst3|counter[12]~I_modesel\ <= "1100010010110";
\inst3|counter[12]~I_pathsel\ <= "01110010011";
\inst3|counter[13]~I_modesel\ <= "1100010010110";
12345

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