trian.vho

FPGA编写的三角波发生器

SIGNAL \inst16|lpm_shiftreg_component|dffs[23]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[23]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[23]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|addr0[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|addr0[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[24]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[24]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[24]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[24]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|addr0[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|addr0[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[25]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[25]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[25]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[25]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|addr0[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|addr0[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[26]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[26]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[26]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[26]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|addr0[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|addr0[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[27]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[27]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[27]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[27]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|addr0[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|addr0[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[28]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[28]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|addr0[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|addr0[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[29]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[29]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|addr0[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|addr0[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|altsyncram_component|auto_generated|q_a[7]~I_modesel\ : std_logic_vector(40 DOWNTO 0);
SIGNAL \inst|altsyncram_component|auto_generated|q_a[6]~I_modesel\ : std_logic_vector(40 DOWNTO 0);
SIGNAL \p33~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \p35~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \swt3~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \swt2~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \tcs~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \treg~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \we~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \clk0out~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \datout[7]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \datout[6]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \datout[5]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \datout[4]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \datout[3]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \datout[2]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \datout[1]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \datout[0]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \inst5|altpll_component|pll~CLK1\ : std_logic;
SIGNAL \inst5|altpll_component|_clk2\ : std_logic;
SIGNAL \inst5|altpll_component|pll~CLK3\ : std_logic;
SIGNAL \inst5|altpll_component|pll~CLK4\ : std_logic;
SIGNAL \inst5|altpll_component|pll~CLK5\ : std_logic;
SIGNAL \inst19~15\ : std_logic;
SIGNAL \datinclk~combout\ : std_logic;
SIGNAL \addrclk~combout\ : std_logic;
SIGNAL \fswclk~combout\ : std_logic;
SIGNAL \senddatclk~combout\ : std_logic;
SIGNAL \cs~combout\ : std_logic;
SIGNAL \clk0~combout\ : std_logic;
SIGNAL \inst5|altpll_component|_clk0\ : std_logic;
SIGNAL \inst10~11\ : std_logic;
SIGNAL \inst4|temp[8]\ : std_logic;
SIGNAL \inst4|Add0~166\ : std_logic;
SIGNAL \inst4|temp[0]\ : std_logic;
SIGNAL \inst4|Add0~167\ : std_logic;
SIGNAL \inst4|Add0~167COUT1_210\ : std_logic;
SIGNAL \inst4|Add0~163\ : std_logic;
SIGNAL \inst4|Add0~163COUT1_212\ : std_logic;
SIGNAL \inst4|Add0~168\ : std_logic;
SIGNAL \inst4|temp[2]\ : std_logic;
SIGNAL \inst4|Add0~169\ : std_logic;
SIGNAL \inst4|Add0~169COUT1_214\ : std_logic;
SIGNAL \inst4|Add0~164\ : std_logic;
SIGNAL \inst4|temp[3]\ : std_logic;
SIGNAL \inst4|Add0~165\ : std_logic;
SIGNAL \inst4|Add0~165COUT1_216\ : std_logic;
SIGNAL \inst4|Add0~170\ : std_logic;
SIGNAL \inst4|temp[4]\ : std_logic;
SIGNAL \inst4|Add0~171\ : std_logic;
SIGNAL \inst4|Add0~172\ : std_logic;
SIGNAL \inst4|temp[5]\ : std_logic;
SIGNAL \inst4|Add0~173\ : std_logic;
SIGNAL \inst4|Add0~173COUT1_218\ : std_logic;
SIGNAL \inst4|Add0~174\ : std_logic;
SIGNAL \inst4|temp[6]\ : std_logic;
SIGNAL \inst4|Add0~175\ : std_logic;
SIGNAL \inst4|Add0~175COUT1_220\ : std_logic;
SIGNAL \inst4|Add0~176\ : std_logic;
SIGNAL \inst4|temp[7]\ : std_logic;
SIGNAL \inst4|Add0~177\ : std_logic;
SIGNAL \inst4|Add0~177COUT1_222\ : std_logic;
SIGNAL \inst4|Add0~178\ : std_logic;
SIGNAL \inst4|temp[9]\ : std_logic;
SIGNAL \inst4|Add0~179\ : std_logic;
SIGNAL \inst4|Add0~179COUT1_224\ : std_logic;
SIGNAL \inst4|Add0~180\ : std_logic;
SIGNAL \inst4|temp[10]\ : std_logic;
SIGNAL \inst4|Add0~181\ : std_logic;
SIGNAL \inst4|Add0~182\ : std_logic;
SIGNAL \inst4|Equal0~141\ : std_logic;
SIGNAL \inst4|Equal0~142\ : std_logic;
SIGNAL \inst4|temp[1]\ : std_logic;
SIGNAL \inst4|Add0~162\ : std_logic;
SIGNAL \inst4|Equal0~140\ : std_logic;
SIGNAL \inst4|clkout\ : std_logic;
SIGNAL \inst11|clk1\ : std_logic;
SIGNAL \wren~combout\ : std_logic;
SIGNAL \datin~combout\ : std_logic;
SIGNAL \inst1|lpm_shiftreg_component|dffs[0]\ : std_logic;
SIGNAL \inst1|lpm_shiftreg_component|dffs[1]\ : std_logic;
SIGNAL \inst1|lpm_shiftreg_component|dffs[2]\ : std_logic;
SIGNAL \inst1|lpm_shiftreg_component|dffs[3]\ : std_logic;
SIGNAL \inst1|lpm_shiftreg_component|dffs[4]\ : std_logic;
SIGNAL \inst1|lpm_shiftreg_component|dffs[5]\ : std_logic;
SIGNAL \inst1|lpm_shiftreg_component|dffs[6]\ : std_logic;
SIGNAL \inst1|lpm_shiftreg_component|dffs[7]\ : std_logic;
SIGNAL \addrdat~combout\ : std_logic;
SIGNAL \inst18|lpm_shiftreg_component|dffs[0]\ : std_logic;
SIGNAL \fswdat~combout\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[0]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[1]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[2]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[3]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[4]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[5]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[6]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[7]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[8]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[9]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[10]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[11]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[12]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[13]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[14]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[15]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[16]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[17]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[18]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[19]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[20]\ : std_logic;
SIGNAL \inst3|counter[0]\ : std_logic;
SIGNAL \inst3|counter[0]~149\ : std_logic;
SIGNAL \inst3|counter[0]~149COUT1_224\ : std_logic;
SIGNAL \inst3|counter[1]\ : std_logic;
SIGNAL \inst3|counter[1]~148\ : std_logic;
SIGNAL \inst3|counter[1]~148COUT1_226\ : std_logic;
SIGNAL \inst3|counter[2]\ : std_logic;
SIGNAL \inst3|counter[2]~147\ : std_logic;
SIGNAL \inst3|counter[2]~147COUT1_228\ : std_logic;
SIGNAL \inst3|counter[3]\ : std_logic;
SIGNAL \inst3|counter[3]~146\ : std_logic;
SIGNAL \inst3|counter[3]~146COUT1_230\ : std_logic;
SIGNAL \inst3|counter[4]\ : std_logic;
SIGNAL \inst3|counter[4]~145\ : std_logic;
SIGNAL \inst3|counter[5]\ : std_logic;
SIGNAL \inst3|counter[5]~144\ : std_logic;
SIGNAL \inst3|counter[5]~144COUT1_232\ : std_logic;
SIGNAL \inst3|counter[6]\ : std_logic;
SIGNAL \inst3|counter[6]~143\ : std_logic;
SIGNAL \inst3|counter[6]~143COUT1_234\ : std_logic;
SIGNAL \inst3|counter[7]\ : std_logic;
SIGNAL \inst3|counter[7]~142\ : std_logic;
SIGNAL \inst3|counter[7]~142COUT1_236\ : std_logic;
SIGNAL \inst3|counter[8]\ : std_logic;
SIGNAL \inst3|counter[8]~141\ : std_logic;
SIGNAL \inst3|counter[8]~141COUT1_238\ : std_logic;
SIGNAL \inst3|counter[9]\ : std_logic;
SIGNAL \inst3|counter[9]~140\ : std_logic;
SIGNAL \inst3|counter[10]\ : std_logic;
SIGNAL \inst3|counter[10]~139\ : std_logic;
SIGNAL \inst3|counter[10]~139COUT1_240\ : std_logic;
SIGNAL \inst3|counter[11]\ : std_logic;
SIGNAL \inst3|counter[11]~138\ : std_logic;
SIGNAL \inst3|counter[11]~138COUT1_242\ : std_logic;
SIGNAL \inst3|counter[12]\ : std_logic;
SIGNAL \inst3|counter[12]~137\ : std_logic;
SIGNAL \inst3|counter[12]~137COUT1_244\ : std_logic;
SIGNAL \inst3|counter[13]\ : std_logic;
SIGNAL \inst3|counter[13]~136\ : std_logic;
SIGNAL \inst3|counter[13]~136COUT1_246\ : std_logic;
SIGNAL \inst3|counter[14]\ : std_logic;
SIGNAL \inst3|counter[14]~135\ : std_logic;
SIGNAL \inst3|counter[15]\ : std_logic;
SIGNAL \inst3|counter[15]~134\ : std_logic;
SIGNAL \inst3|counter[15]~134COUT1_248\ : std_logic;
SIGNAL \inst3|counter[16]\ : std_logic;
SIGNAL \inst3|counter[16]~133\ : std_logic;
SIGNAL \inst3|counter[16]~133COUT1_250\ : std_logic;
SIGNAL \inst3|counter[17]\ : std_logic;
SIGNAL \inst3|counter[17]~132\ : std_logic;
SIGNAL \inst3|counter[17]~132COUT1_252\ : std_logic;
SIGNAL \inst3|counter[18]\ : std_logic;
SIGNAL \inst3|counter[18]~131\ : std_logic;
SIGNAL \inst3|counter[18]~131COUT1_254\ : std_logic;
SIGNAL \inst3|counter[19]\ : std_logic;
SIGNAL \inst3|counter[19]~130\ : std_logic;
SIGNAL \inst3|counter[20]\ : std_logic;
SIGNAL \inst2|addr0[0]\ : std_logic;
SIGNAL \inst18|lpm_shiftreg_component|dffs[1]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[21]\ : std_logic;
SIGNAL \inst3|counter[20]~120\ : std_logic;
SIGNAL \inst3|counter[20]~120COUT1_256\ : std_logic;
SIGNAL \inst3|counter[21]\ : std_logic;
SIGNAL \inst2|addr0[1]\ : std_logic;
SIGNAL \inst18|lpm_shiftreg_component|dffs[2]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[22]\ : std_logic;
SIGNAL \inst3|counter[21]~121\ : std_logic;
SIGNAL \inst3|counter[21]~121COUT1_258\ : std_logic;
SIGNAL \inst3|counter[22]\ : std_logic;
SIGNAL \inst2|addr0[2]\ : std_logic;
SIGNAL \inst18|lpm_shiftreg_component|dffs[3]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[23]\ : std_logic;
SIGNAL \inst3|counter[22]~122\ : std_logic;
SIGNAL \inst3|counter[22]~122COUT1_260\ : std_logic;
SIGNAL \inst3|counter[23]\ : std_logic;
SIGNAL \inst2|addr0[3]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[24]\ : std_logic;
SIGNAL \inst3|counter[23]~123\ : std_logic;
SIGNAL \inst3|counter[23]~123COUT1_262\ : std_logic;
SIGNAL \inst3|counter[24]\ : std_logic;
SIGNAL \inst18|lpm_shiftreg_component|dffs[4]\ : std_logic;
SIGNAL \inst2|addr0[4]\ : std_logic;
SIGNAL \inst18|lpm_shiftreg_component|dffs[5]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[25]\ : std_logic;
SIGNAL \inst3|counter[24]~124\ : std_logic;
SIGNAL \inst3|counter[25]\ : std_logic;
SIGNAL \inst2|addr0[5]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[26]\ : std_logic;
SIGNAL \inst3|counter[25]~125\ : std_logic;
SIGNAL \inst3|counter[25]~125COUT1_264\ : std_logic;
SIGNAL \inst3|counter[26]\ : std_logic;
SIGNAL \inst18|lpm_shiftreg_component|dffs[6]\ : std_logic;
SIGNAL \inst2|addr0[6]\ : std_logic;
SIGNAL \inst16|lpm_shiftreg_component|dffs[27]\ : std_logic;
SIGNAL \inst3|counter[26]~126\ : std_logic;
SIGNAL \inst3|counter[26]~126COUT1_266\ : std_logic;
SIGNAL \inst3|counter[27]\ : std_logic;
SIGNAL \inst18|lpm_shiftreg_component|dffs[7]\ : std_logic;
SIGNAL \inst2|addr0[7]\ : std_logic;
SIGNAL \inst3|counter[27]~127\ : std_logic;
SIGNAL \inst3|counter[27]~127COUT1_268\ : std_logic;
SIGNAL \inst3|counter[28]\ : std_logic;
SIGNAL \inst18|lpm_shiftreg_component|dffs[8]\ : std_logic;
SIGNAL \inst2|addr0[8]\ : std_logic;
SIGNAL \inst3|counter[28]~128\ : std_logic;
SIGNAL \inst3|counter[28]~128COUT1_270\ : std_logic;
SIGNAL \inst3|counter[29]\ : std_logic;
SIGNAL \inst18|lpm_shiftreg_component|dffs[9]\ : std_logic;
SIGNAL \inst2|addr0[9]\ : std_logic;
SIGNAL \inst|altsyncram_component|auto_generated|q_a[7]\ : std_logic;
SIGNAL \inst|altsyncram_component|auto_generated|q_a[6]\ : std_logic;
SIGNAL \inst|altsyncram_component|auto_generated|q_a[5]\ : std_logic;
SIGNAL \inst|altsyncram_component|auto_generated|q_a[4]\ : std_logic;
SIGNAL \inst|altsyncram_component|auto_generated|q_a[3]\ : std_logic;
SIGNAL \inst|altsyncram_component|auto_generated|q_a[2]\ : std_logic;
SIGNAL \inst|altsyncram_component|auto_generated|q_a[1]\ : std_logic;
SIGNAL \inst|altsyncram_component|auto_generated|q_a[0]\ : std_logic;
COMPONENT cyclone_lcell
PORT (
	clk : IN STD_LOGIC;