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📄 trian.vho

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-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

-- DATE "08/23/2007 15:59:29"

-- 
-- Device: Altera EP1C3T144C8 Package TQFP144
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	trian IS
    PORT (
	p33 : OUT std_logic;
	clk0 : IN std_logic;
	p35 : OUT std_logic;
	swt3 : OUT std_logic;
	swt2 : OUT std_logic;
	tcs : OUT std_logic;
	treg : OUT std_logic;
	we : OUT std_logic;
	cs : IN std_logic;
	senddatclk : IN std_logic;
	clk0out : OUT std_logic;
	datout : OUT std_logic_vector(7 DOWNTO 0);
	wren : IN std_logic;
	fswclk : IN std_logic;
	fswdat : IN std_logic;
	addrclk : IN std_logic;
	addrdat : IN std_logic;
	datinclk : IN std_logic;
	datin : IN std_logic
	);
END trian;

ARCHITECTURE structure OF trian IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_p33 : std_logic;
SIGNAL ww_clk0 : std_logic;
SIGNAL ww_p35 : std_logic;
SIGNAL ww_swt3 : std_logic;
SIGNAL ww_swt2 : std_logic;
SIGNAL ww_tcs : std_logic;
SIGNAL ww_treg : std_logic;
SIGNAL ww_we : std_logic;
SIGNAL ww_cs : std_logic;
SIGNAL ww_senddatclk : std_logic;
SIGNAL ww_clk0out : std_logic;
SIGNAL ww_datout : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_wren : std_logic;
SIGNAL ww_fswclk : std_logic;
SIGNAL ww_fswdat : std_logic;
SIGNAL ww_addrclk : std_logic;
SIGNAL ww_addrdat : std_logic;
SIGNAL ww_datinclk : std_logic;
SIGNAL ww_datin : std_logic;
SIGNAL \inst|altsyncram_component|auto_generated|q_a[7]~I_PORTADATAIN_bus\ : std_logic_vector(143 DOWNTO 0);
SIGNAL \inst|altsyncram_component|auto_generated|q_a[7]~I_PORTAADDR_bus\ : std_logic_vector(15 DOWNTO 0);
SIGNAL \inst|altsyncram_component|auto_generated|q_a[7]~I_PORTADATAOUT_bus\ : std_logic_vector(143 DOWNTO 0);
SIGNAL \inst|altsyncram_component|auto_generated|q_a[6]~I_PORTADATAIN_bus\ : std_logic_vector(143 DOWNTO 0);
SIGNAL \inst|altsyncram_component|auto_generated|q_a[6]~I_PORTAADDR_bus\ : std_logic_vector(15 DOWNTO 0);
SIGNAL \inst|altsyncram_component|auto_generated|q_a[6]~I_PORTADATAOUT_bus\ : std_logic_vector(143 DOWNTO 0);
SIGNAL \inst5|altpll_component|_clk0~I_INCLK_bus\ : std_logic_vector(1 DOWNTO 0);
SIGNAL \inst5|altpll_component|_clk0~I_CLKENA_bus\ : std_logic_vector(5 DOWNTO 0);
SIGNAL \inst5|altpll_component|_clk0~I_CLK_bus\ : std_logic_vector(5 DOWNTO 0);
SIGNAL \datinclk~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \inst19~15_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst19~15_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \addrclk~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \fswclk~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \senddatclk~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \cs~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \clk0~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \inst10~11_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst10~11_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|temp[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|temp[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|Add0~166_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|Add0~166_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|temp[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|temp[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|Add0~162_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|Add0~162_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|Add0~168_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|Add0~168_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|temp[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|temp[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|Add0~164_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|Add0~164_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|temp[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|temp[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|Add0~170_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|Add0~170_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|temp[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|temp[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|Add0~172_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|Add0~172_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|temp[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|temp[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|Add0~174_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|Add0~174_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|temp[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|temp[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|Add0~176_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|Add0~176_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|temp[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|temp[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|Add0~178_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|Add0~178_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|temp[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|temp[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|Add0~180_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|Add0~180_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|temp[10]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|temp[10]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|Add0~182_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|Add0~182_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|Equal0~141_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|Equal0~141_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|Equal0~142_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|Equal0~142_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|temp[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|temp[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|Equal0~140_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|Equal0~140_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst4|clkout~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst4|clkout~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst11|clk1~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst11|clk1~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \wren~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \datin~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst1|lpm_shiftreg_component|dffs[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \addrdat~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \fswdat~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[10]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[10]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[11]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[11]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[12]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[12]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[13]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[13]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[14]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[14]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[15]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[15]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[16]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[16]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[17]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[17]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[18]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[18]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[19]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[19]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[20]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[20]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[10]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[10]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[11]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[11]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[12]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[12]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[13]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[13]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[14]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[14]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[15]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[15]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[16]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[16]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[17]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[17]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[18]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[18]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[19]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[19]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[20]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[20]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|addr0[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|addr0[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[21]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[21]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[21]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[21]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|addr0[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|addr0[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[22]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[22]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst3|counter[22]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst3|counter[22]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst2|addr0[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst2|addr0[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst18|lpm_shiftreg_component|dffs[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst16|lpm_shiftreg_component|dffs[23]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
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