📄 trian_vhd.sdo

📁 FPGA编写的三角波发生器
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    (DELAY
      (ABSOLUTE
        (PORT datad (516:516:516) (516:516:516))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst1\|lpm_shiftreg_component\|dffs\[3\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4861:4861:4861) (4861:4861:4861))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst1\|lpm_shiftreg_component\|dffs\[4\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (543:543:543) (543:543:543))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst1\|lpm_shiftreg_component\|dffs\[4\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datain (658:658:658) (658:658:658))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4861:4861:4861) (4861:4861:4861))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst1\|lpm_shiftreg_component\|dffs\[5\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (522:522:522) (522:522:522))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst1\|lpm_shiftreg_component\|dffs\[5\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4861:4861:4861) (4861:4861:4861))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst1\|lpm_shiftreg_component\|dffs\[6\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (546:546:546) (546:546:546))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst1\|lpm_shiftreg_component\|dffs\[6\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datain (661:661:661) (661:661:661))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4861:4861:4861) (4861:4861:4861))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst1\|lpm_shiftreg_component\|dffs\[7\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (547:547:547) (547:547:547))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst1\|lpm_shiftreg_component\|dffs\[7\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datain (662:662:662) (662:662:662))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4861:4861:4861) (4861:4861:4861))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE \\addrdat\~I\\.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst18\|lpm_shiftreg_component\|dffs\[0\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (6037:6037:6037) (6037:6037:6037))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst18\|lpm_shiftreg_component\|dffs\[0\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4909:4909:4909) (4909:4909:4909))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE \\fswdat\~I\\.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[0\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (6024:6024:6024) (6024:6024:6024))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[0\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (5350:5350:5350) (5350:5350:5350))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[1\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (542:542:542) (542:542:542))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[1\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datain (657:657:657) (657:657:657))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (5350:5350:5350) (5350:5350:5350))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[2\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (514:514:514) (514:514:514))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[2\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (5350:5350:5350) (5350:5350:5350))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[3\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (521:521:521) (521:521:521))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[3\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (5350:5350:5350) (5350:5350:5350))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[4\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (544:544:544) (544:544:544))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[4\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datain (659:659:659) (659:659:659))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (5350:5350:5350) (5350:5350:5350))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[5\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (518:518:518) (518:518:518))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[5\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (5350:5350:5350) (5350:5350:5350))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[6\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (543:543:543) (543:543:543))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[6\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datain (658:658:658) (658:658:658))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (5350:5350:5350) (5350:5350:5350))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[7\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (544:544:544) (544:544:544))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[7\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datain (659:659:659) (659:659:659))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (5350:5350:5350) (5350:5350:5350))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[8\]\~I\\.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (1290:1290:1290) (1290:1290:1290))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[8\]\~I\\.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datain (1405:1405:1405) (1405:1405:1405))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (5350:5350:5350) (5350:5350:5350))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE \\inst16\|lpm_shiftreg_component\|dffs\[9\]\~I\\.lecomb)
    (DELAY
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