fenpin.v

来自「FPGA编写的三角波发生器」· Verilog 代码 · 共 20 行

module fenpin(tcs,treg,clk1,p33,p35,swt3,swt2,clk0);
input clk0;
output clk1;
output p33,p35,swt2,swt3,tcs,treg;
reg p33,p35,swt2,swt3,tcs,treg;
reg clk1;
always@(posedge clk0)
begin
	clk1=~clk1;
end
always@(clk0)
begin
    p33=0;
	p35=0;
	swt2=1;
	swt3=1;
	tcs=0;
	treg=0;
end
endmodule