trian.eda.rpt

来自「FPGA编写的三角波发生器」· RPT 代码 · 共 86 行

EDA Netlist Writer report for trian
Thu Aug 23 15:59:29 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. Timing Analysis Settings
  4. Timing Analysis Generated Files
  5. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; EDA Netlist Writer Summary                                             ;
+--------------------------------+---------------------------------------+
; EDA Netlist Writer Status      ; Successful - Thu Aug 23 15:59:29 2007 ;
; Revision Name                  ; trian                                 ;
; Top-level Entity Name          ; trian                                 ;
; Family                         ; Cyclone                               ;
; Timing Analysis Files Creation ; Successful                            ;
+--------------------------------+---------------------------------------+


+--------------------------------------------------------+
; Timing Analysis Settings                               ;
+-------------------------------------+------------------+
; Option                              ; Setting          ;
+-------------------------------------+------------------+
; Tool Name                           ; PrimeTime (VHDL) ;
; Time scale                          ; 1 ps             ;
; Truncate long hierarchy paths       ; Off              ;
; Map illegal HDL characters          ; Off              ;
; Flatten buses into individual nodes ; Off              ;
+-------------------------------------+------------------+


+--------------------------------------------------------+
; Timing Analysis Generated Files                        ;
+--------------------------------------------------------+
; Generated Files                                        ;
+--------------------------------------------------------+
; F:/altera/可调三角波/timing/primetime/trian.vho        ;
; F:/altera/可调三角波/timing/primetime/trian_vhd.sdo    ;
; F:/altera/可调三角波/timing/primetime/trian_pt_vhd.tcl ;
+--------------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Aug 23 15:59:28 2007
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off trian -c trian
Info: Generated files "trian.vho" and "trian_vhd.sdo" in directory "F:/altera/可调三角波/timing/primetime/" for EDA timing analysis tool
Info: Generated PrimeTime Tcl script file F:/altera/可调三角波/timing/primetime/trian_pt_vhd.tcl
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Aug 23 15:59:29 2007
    Info: Elapsed time: 00:00:01