trian.tan.summary

来自「FPGA编写的三角波发生器」· SUMMARY 代码 · 共 127 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.517 ns
From           : wren
To             : wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a7~porta_we_reg
From Clock     : --
To Clock       : clk0
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.146 ns
From           : wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|q_a[6]
To             : datout[6]
From Clock     : cs
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.927 ns
From           : wren
To             : wave:inst|altsyncram:altsyncram_component|altsyncram_aaa1:auto_generated|ram_block1a6~porta_we_reg
From Clock     : --
To Clock       : cs
Failed Paths   : 0

Type           : Clock Setup: 'pll:inst5|altpll:altpll_component|_clk0'
Slack          : -1.449 ns
Required Time  : 256.02 MHz ( period = 3.906 ns )
Actual Time    : 186.74 MHz ( period = 5.355 ns )
From           : sinwave:inst4|temp[1]
To             : sinwave:inst4|temp[3]
From Clock     : pll:inst5|altpll:altpll_component|_clk0
To Clock       : pll:inst5|altpll:altpll_component|_clk0
Failed Paths   : 114

Type           : Clock Setup: 'clk0'
Slack          : 61.225 ns
Required Time  : 16.00 MHz ( period = 62.500 ns )
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : fenpin:inst11|clk1
To             : fenpin:inst11|clk1
From Clock     : clk0
To Clock       : clk0
Failed Paths   : 0

Type           : Clock Setup: 'cs'
Slack          : N/A
Required Time  : None
Actual Time    : 186.74 MHz ( period = 5.355 ns )
From           : sinwave:inst4|temp[1]
To             : sinwave:inst4|temp[3]
From Clock     : cs
To Clock       : cs
Failed Paths   : 0

Type           : Clock Setup: 'fswclk'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : fsw:inst16|lpm_shiftreg:lpm_shiftreg_component|dffs[10]
To             : fsw:inst16|lpm_shiftreg:lpm_shiftreg_component|dffs[11]
From Clock     : fswclk
To Clock       : fswclk
Failed Paths   : 0

Type           : Clock Setup: 'addrclk'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : dat:inst18|lpm_shiftreg:lpm_shiftreg_component|dffs[4]
To             : dat:inst18|lpm_shiftreg:lpm_shiftreg_component|dffs[5]
From Clock     : addrclk
To Clock       : addrclk
Failed Paths   : 0

Type           : Clock Setup: 'datinclk'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[4]
To             : datin:inst1|lpm_shiftreg:lpm_shiftreg_component|dffs[5]
From Clock     : datinclk
To Clock       : datinclk
Failed Paths   : 0

Type           : Clock Hold: 'clk0'
Slack          : 1.223 ns
Required Time  : 16.00 MHz ( period = 62.500 ns )
Actual Time    : N/A
From           : fenpin:inst11|clk1
To             : fenpin:inst11|clk1
From Clock     : clk0
To Clock       : clk0
Failed Paths   : 0

Type           : Clock Hold: 'pll:inst5|altpll:altpll_component|_clk0'
Slack          : 1.314 ns
Required Time  : 256.02 MHz ( period = 3.906 ns )
Actual Time    : N/A
From           : sinwave:inst4|clkout
To             : sinwave:inst4|clkout
From Clock     : pll:inst5|altpll:altpll_component|_clk0
To Clock       : pll:inst5|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 114

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