write.vhd

自己写的代码 能用 关于写I2C方面的 应该还不错的

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:02:56 02/04/2007 
-- Design Name: 
-- Module Name:    write - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity write is
	port(clk: in std_logic;
		  rst: in std_logic;
		  wr:  in std_logic;
		  rd:  in std_logic;
		  addr:in std_logic_vector(10 downto 0);
		  data_w:in std_logic_vector(7 downto 0);
		  data_r:out std_logic_vector(7 downto 0);
		  ack: out std_logic;
		  scl: out std_logic;
		  sda: inout std_logic);
end write;

architecture Behavioral of write is

signal ack_s:std_logic;
signal scl_s:std_logic;
signal wf:std_logic;
signal rf:std_logic;
signal ff:std_logic;
signal head_buf:std_logic_vector(1 downto 0);
signal stop_buf:std_logic_vector(1 downto 0);
signal sh8out_buf:std_logic_vector(7 downto 0);
signal sh8out_state:std_logic_vector(8 downto 0);
signal sh8in_state:std_logic_vector(9 downto 0);
signal head_state:std_logic_vector(2 downto 0);
signal stop_state:std_logic_vector(2 downto 0);
signal main_state:std_logic_vector(10 downto 0);
signal data_r_s:std_logic_vector(7 downto 0);
signal link_sda:std_logic;
signal link_head:std_logic;
signal link_write:std_logic;
signal link_stop:std_logic;
signal sda1:std_logic;
signal sda2:std_logic;
signal sda3:std_logic;
signal sda4:std_logic;
--signal rd_ack:std_logic;


CONSTANT  Idle                  :  std_logic_vector(10 DOWNTO 0) := "00000000001";    
CONSTANT  Ready                 :  std_logic_vector(10 DOWNTO 0) := "00000000010";    
CONSTANT  Write_start           :  std_logic_vector(10 DOWNTO 0) := "00000000100";    
CONSTANT  Ctrl_write            :  std_logic_vector(10 DOWNTO 0) := "00000001000";    
CONSTANT  Addr_write            :  std_logic_vector(10 DOWNTO 0) := "00000010000";    
CONSTANT  Data_write            :  std_logic_vector(10 DOWNTO 0) := "00000100000";    
CONSTANT  Read_start            :  std_logic_vector(10 DOWNTO 0) := "00001000000";    
CONSTANT  Ctrl_read             :  std_logic_vector(10 DOWNTO 0) := "00010000000";    
CONSTANT  Data_read             :  std_logic_vector(10 DOWNTO 0) := "00100000000";    
CONSTANT  Stop                  :  std_logic_vector(10 DOWNTO 0) := "01000000000";    
CONSTANT  Ackn                  :  std_logic_vector(10 DOWNTO 0) := "10000000000";    
CONSTANT  sh8out_bit7           :  std_logic_vector(8 DOWNTO 0) := "000000001";    
CONSTANT  sh8out_bit6           :  std_logic_vector(8 DOWNTO 0) := "000000010";    
CONSTANT  sh8out_bit5           :  std_logic_vector(8 DOWNTO 0) := "000000100";    
CONSTANT  sh8out_bit4           :  std_logic_vector(8 DOWNTO 0) := "000001000";    
CONSTANT  sh8out_bit3           :  std_logic_vector(8 DOWNTO 0) := "000010000";    
CONSTANT  sh8out_bit2           :  std_logic_vector(8 DOWNTO 0) := "000100000";    
CONSTANT  sh8out_bit1           :  std_logic_vector(8 DOWNTO 0) := "001000000";    
CONSTANT  sh8out_bit0           :  std_logic_vector(8 DOWNTO 0) := "010000000";    
CONSTANT  sh8out_end            :  std_logic_vector(8 DOWNTO 0) := "100000000";    
CONSTANT  sh8in_begin           :  std_logic_vector(9 DOWNTO 0) := "0000000001";    
CONSTANT  sh8in_bit7            :  std_logic_vector(9 DOWNTO 0) := "0000000010";    
CONSTANT  sh8in_bit6            :  std_logic_vector(9 DOWNTO 0) := "0000000100";    
CONSTANT  sh8in_bit5            :  std_logic_vector(9 DOWNTO 0) := "0000001000";    
CONSTANT  sh8in_bit4            :  std_logic_vector(9 DOWNTO 0) := "0000010000";    
CONSTANT  sh8in_bit3            :  std_logic_vector(9 DOWNTO 0) := "0000100000";    
CONSTANT  sh8in_bit2            :  std_logic_vector(9 DOWNTO 0) := "0001000000";    
CONSTANT  sh8in_bit1            :  std_logic_vector(9 DOWNTO 0) := "0010000000";    
CONSTANT  sh8in_bit0            :  std_logic_vector(9 DOWNTO 0) := "0100000000";    
CONSTANT  sh8in_end             :  std_logic_vector(9 DOWNTO 0) := "1000000000";    
CONSTANT  head_begin            :  std_logic_vector(2 DOWNTO 0) := "001";    
CONSTANT  head_bit              :  std_logic_vector(2 DOWNTO 0) := "010";    
CONSTANT  head_end              :  std_logic_vector(2 DOWNTO 0) := "100";    
CONSTANT  stop_begin            :  std_logic_vector(2 DOWNTO 0) := "001";    
CONSTANT  stop_bit              :  std_logic_vector(2 DOWNTO 0) := "010";    
CONSTANT  stop_end              :  std_logic_vector(2 DOWNTO 0) := "100";    
CONSTANT  YES                   :  std_logic := '1';    
CONSTANT  NO                    :  std_logic := '0';  

------------------------------------------------------------
procedure shift8in is
	begin
		case sh8in_state is
			when sh8in_begin=>
				sh8in_state	<=sh8in_bit7;
			when sh8in_bit7=>
				if (scl_s='1') then				
					data_r_s(7)	<=sda;
					sh8in_state	<=sh8in_bit6;				
			   else
					sh8in_state	<=sh8in_bit7;
				end if;
			when sh8in_bit6=>
				if (scl_s='1') then				
					data_r_s(6)	<=sda;
					sh8in_state	<=sh8in_bit5;				
			   else
					sh8in_state	<=sh8in_bit6;
				end if;
			when sh8in_bit5=>
				if (scl_s='1') then				
					data_r_s(5)	<=sda;
					sh8in_state	<=sh8in_bit4;				
			   else
					sh8in_state	<=sh8in_bit5;
				end if;
			when sh8in_bit4=>
				if (scl_s='1') then				
					data_r_s(4)	<=sda;
					sh8in_state	<=sh8in_bit3;				
			   else
					sh8in_state	<=sh8in_bit4;
				end if;
			when sh8in_bit3=>
				if (scl_s='1') then				
					data_r_s(3)	<=sda;
					sh8in_state	<=sh8in_bit2;				
			   else
					sh8in_state	<=sh8in_bit3;
				end if;
			when sh8in_bit2=>
				if (scl_s='1') then 				
					data_r_s(2)	<=sda;
					sh8in_state	<=sh8in_bit1;				
			   else
					sh8in_state	<=sh8in_bit2;
				end if;
			when sh8in_bit1=>
				if (scl_s='1') then				
					data_r_s(1)	<=sda;
					sh8in_state	<=sh8in_bit0;				
			   else
					sh8in_state	<=sh8in_bit1;
				end if;
			when sh8in_bit0=>
				if (scl_s='1') then				
					data_r_s(0)	<=sda;
					sh8in_state	<=sh8in_end;				
			   else
					sh8in_state	<=sh8in_bit0;
				end if;
			when sh8in_end=>
				if (scl_s='1') then	
					ff		<='1';
					sh8in_state	<=sh8in_bit7;
				else
					sh8in_state	<=sh8in_end;
				end if;
			when others=>			
				sh8in_state	<=sh8in_bit7;			
		end case;	
end shift8in;
-----------------------------------------------------------
procedure shift8_out is
	begin
		case sh8out_state is
			when sh8out_bit7=>
				if (scl_s='0') then					
					link_sda	<=YES;
					link_write	<=YES;
					sh8out_state	<=sh8out_bit6;					
				else
					sh8out_state	<=sh8out_bit7;
				end if;
			when sh8out_bit6=>
				if(scl_s='0') then					
					link_sda	<=YES;
					link_write	<=YES;
					sh8out_state	<=sh8out_bit5;
					--sh8out_buf	<=ShiftLeft(sh8out_buf, 1);
					sh8out_buf(7)	<=sh8out_buf(6);
					--sh8out_buf<=sh8out_buf sll 1;
				else
					sh8out_state	<=sh8out_bit6;
				end if;
			when sh8out_bit5=>
				if (scl_s='0') then					
					sh8out_state	<=sh8out_bit4;
					--sh8out_buf	<=ShiftLeft(sh8out_buf, 1);
					sh8out_buf(7)	<=sh8out_buf(5);
				else
					sh8out_state	<=sh8out_bit5;
				end if;
			when sh8out_bit4=>
				if (scl_s='0') then					
					sh8out_state	<=sh8out_bit3;
					--sh8out_buf	<=ShiftLeft(sh8out_buf, 1);
					sh8out_buf(7)	<=sh8out_buf(4);
				else
					sh8out_state	<=sh8out_bit4;
				end if;
			when sh8out_bit3=>
				if (scl_s='0') then					
					sh8out_state	<=sh8out_bit2;
					--sh8out_buf	<=ShiftLeft(sh8out_buf, 1);
					sh8out_buf(7)	<=sh8out_buf(3);
				else
					sh8out_state	<=sh8out_bit3;
				end if;
			when sh8out_bit2=>
				if (scl_s='0') then					
					sh8out_state	<=sh8out_bit1;
					--sh8out_buf	<=ShiftLeft(sh8out_buf, 1);
					sh8out_buf(7)	<=sh8out_buf(2);
				else
					sh8out_state	<=sh8out_bit2;
				end if;
			when sh8out_bit1=>
				if (scl_s='0') then					
					sh8out_state	<=sh8out_bit0;
					--sh8out_buf	<=ShiftLeft(sh8out_buf, 1);
					sh8out_buf(7)	<=sh8out_buf(1);
				else
					sh8out_state	<=sh8out_bit1;
				end if;
			when sh8out_bit0=>
				if (scl_s='0') then				
					sh8out_state	<=sh8out_end;
					--sh8out_buf	<=ShiftLeft(sh8out_buf, 1);	
					sh8out_buf(7)	<=sh8out_buf(0);
				else
					sh8out_state	<=sh8out_bit0;
				end if;
			when sh8out_end=>
				if (scl_s='0') then					
					link_sda	<=NO;
					link_write	<=NO;
					ff		<='1';					
				else
					sh8out_state	<=sh8out_end;
				end if;
			when others=>null;
		end case;
end shift8_out;

------------------------------------------------------------------
procedure shift_head is
	begin
		case head_state is
			when head_begin=>
				if (scl_s='0') then				
					link_write	<=NO;
					link_sda	<=YES;
					link_head	<=YES;
					head_state	<=head_bit;				
				else
					head_state	<=head_begin;
				end if;
			when head_bit=>
				if (scl_s='1') then				
					ff		<='1';
					--head_buf	<=head_buf<<1;
					head_buf(1)<=head_buf(0);
					head_state	<=head_end;				
				else
					head_state	<=head_bit;
				end if;
			when head_end=>
				if(scl_s='0') then				
					link_head	<=NO;
					link_write	<=YES;				
				else
					head_state	<=head_end;
				end if;
			when others=>null;
		end case;
end shift_head;
-----------------------------------------------------------------------
procedure shift_stop is
	begin
		case stop_state is 
			when stop_begin=>
				if(scl_s='0') then					
					link_sda	<=YES;
					link_write	<=NO;
					link_stop	<=YES;
					stop_state	<=stop_bit;					
				else
					stop_state	<=stop_begin;
				end if;
			when stop_bit=>
				if (scl_s='1') then					
					--stop_buf	<=ShiftLeft(stop_buf, 1);
					stop_buf(1)<=stop_buf(0);
					stop_state	<=stop_end;					
				else
					stop_state	<=stop_bit;
				end if;
			when stop_end=>
				if (scl_s='0') then					
					link_head	<=NO;
					link_stop	<=NO;
					link_sda	<=NO;
					ff		<='1';					
				else
					stop_state	<=stop_end;
				end if;
			when others=>null;
		end case;
end shift_stop;

begin

sda1<=head_buf(1) when link_head='1' else '0';
sda2<=sh8out_buf(7) when link_write='1' else '0';
sda3<=stop_buf(1) when link_stop='1' else '0';
sda4<=sda1 or sda2 or sda3;
sda<=sda4 when link_sda='1' else 'Z';  

process(clk,rst)
begin
	if(rst='1') then
		scl_s<='0';
	elsif falling_edge(clk) then
		scl_s<=not scl_s;
	end if;
end process;


process(clk,rst)
begin
	if(rst='1') then
		link_write  <=NO;
		link_head	<=NO;
		link_stop	<=NO;
		link_sda	   <=NO;
		ack_s		   <='0';
		rf		      <='0';
		wf		      <='0';
		ff		      <='0';
		head_buf <= "00";
		main_state	<=Idle;
	elsif rising_edge(clk) then
		case main_state is
			when Idle=>
				--rd_ack	 <=NO;
				link_write<=NO;
				link_head <=NO;
				link_stop <=NO;
				link_sda	 <=NO;
				if (wr='1') then
					wf<='1';
					main_state<=Ready;
				elsif (rd='1') then
					rf<='1';
					main_state<=Ready;
				else
					wf<='0';
					rf<='0';
					main_state<=Idle;
				end if;
			when Ready=>		
				link_write	<=NO;
				link_stop	<=NO;
				link_head	<=YES;
				link_sda	   <=YES;
				head_buf <= "10";    
            stop_buf <= "01"; 
				head_state	<=head_begin;
				ff		<='0';
				ack_s	<='0';
				main_state	<=Write_start;			
			when Write_start=>
				if( ff='0') then
					shift_head;
				else				
					sh8out_buf <= '1' & '0' & '1' & '0' & addr(10 DOWNTO 8) & '0';
					link_head	<=NO;
					link_write	<=YES;
					ff				<='0';
					sh8out_state<=sh8out_bit6;
					main_state	<=Ctrl_write;
				end if;
			when Ctrl_write=>
				if (ff='0') then
					shift8_out;
				else					
					sh8out_state <= sh8out_bit7;   
               sh8out_buf <= addr(7 downto 0); 
					ff					<='0';
					main_state	<=Addr_write;
				end if;
			when Addr_write=>
				if (ff='0') then
					shift8_out;
				else				
					ff	<='0';
					if (wf='1') then						
							sh8out_state	<=sh8out_bit7;
							sh8out_buf <= data_w;
							main_state	<=Data_write;
					end if;
					if (rf='1')	then					
							head_buf	<="10";
							head_state	<=head_begin;
							main_state	<=Read_start;
					end if;
				end if;				
			when Data_write=>
				if (ff='0') then
					shift8_out;
				else				
					stop_state	<=stop_begin;
					main_state	<=Stop;
					link_write	<=NO;
					ff		<='0';
				end if;
			when Read_start=>
				if (ff='0') then
					shift_head;
				else				
					sh8out_buf <= '1' & '0' & '1' & '0' & addr(10 DOWNTO 8) & '1';
					link_head	<=NO;
					link_sda	<=YES;
					link_write	<=YES;
					ff		<='0';
					sh8out_state	<=sh8out_bit6;
					main_state	<=Ctrl_read;
				end if;
			when Ctrl_read=>
				if (ff='0') then
					shift8_out;
				else				
					link_sda	<=NO;
					link_write	<=NO;
					ff		<='0';
					sh8in_state	<=sh8in_begin;
					main_state	<=Data_read;
				end if;
			when Data_read=>
				if (ff='0') then
					shift8in;
				else	
					link_stop	<=YES;
					link_sda	<=YES;
					stop_state	<=stop_bit;
					ff		<='0';
					main_state	<=Stop;
				end if;
			when Stop=>
				if (ff='0') then
					shift_stop;
				else				
					ack_s		<='1';
					ff		<='0';
					main_state	<=Ackn;
				end if;
			when Ackn=>			
				ack_s		<='0';
				wf		<='0';
				rf		<='0';
				main_state	<=Idle;			
			when others=>
				main_state	<=Idle;
		end case;
	end if;
end process;

scl<=scl_s;
ack<=ack_s;
data_r<=data_r_s;

end Behavioral;