top.vhd

自己写的代码 能用 关于写I2C方面的 应该还不错的

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:01:56 02/04/2007 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY top IS
   PORT (
      clk                     : IN std_logic;   
      rst                     : IN std_logic;   
      sda                     : INOUT std_logic;   
      scl                     : OUT std_logic;   
      seg:out std_logic_vector(6 downto 0);
		sel:out std_logic_vector(3 downto 0));  
END top;

architecture Behavioral of top is


SIGNAL wr                       :  std_logic;   
SIGNAL rd                       :  std_logic;   
SIGNAL addr                     :  std_logic_vector(10 DOWNTO 0);   
SIGNAL data_w                   :  std_logic_vector(7 DOWNTO 0);   
SIGNAL ack                      :  std_logic;   
SIGNAL data_r                   :  std_logic_vector(7 DOWNTO 0);   
SIGNAL data_rep                 :  std_logic_vector(15 DOWNTO 0);   
SIGNAL show_ok                  :  std_logic;   
SIGNAL wr_flag                  :  std_logic;   
SIGNAL cs                       :  std_logic_vector(6 DOWNTO 0);   
SIGNAL ns                       :  std_logic_vector(6 DOWNTO 0);
SIGNAL clk_cnt                  :  std_logic_vector(11 DOWNTO 0);   
SIGNAL clk_div_cnt              :  std_logic_vector(12 DOWNTO 0);   
SIGNAL clk_div                  :  std_logic;   

   
CONSTANT  IDLE                  :  std_logic_vector(6 DOWNTO 0) := "0000001";    
CONSTANT  WR_BYTE               :  std_logic_vector(6 DOWNTO 0) := "0000010";    
CONSTANT  WR_ACK                :  std_logic_vector(6 DOWNTO 0) := "0000100";    
CONSTANT  DELAY                 :  std_logic_vector(6 DOWNTO 0) := "0001000";    
CONSTANT  RD_BYTE               :  std_logic_vector(6 DOWNTO 0) := "0010000";    
CONSTANT  RD_ACK                :  std_logic_vector(6 DOWNTO 0) := "0100000";    
CONSTANT  SHOW                  :  std_logic_vector(6 DOWNTO 0) := "1000000"; 

component display
	port(clk:in std_logic;
		  data:in std_logic_vector(15 downto 0);
		  seg:out std_logic_vector(6 downto 0);
		  sel:out std_logic_vector(3 downto 0));
end component; 

component write 
	port(clk: in std_logic;
		  rst: in std_logic;
		  wr:  in std_logic;
		  rd:  in std_logic;
		  addr:in std_logic_vector(10 downto 0);
		  data_w:in std_logic_vector(7 downto 0);
		  data_r:out std_logic_vector(7 downto 0);
		  ack: out std_logic;
		  scl: out std_logic;
		  sda: inout std_logic);
end component;  

begin

PROCESS(clk,rst)
BEGIN
	if (rst='1') then      
		clk_cnt <= "000000000000";    
   elsif rising_edge(clk) then
		IF (clk_cnt = "010011100010") THEN
			clk_cnt <= "000000000000";    
      ELSE
         clk_cnt <= clk_cnt + 1;    
      END IF;
   END IF;
END PROCESS;

PROCESS(clk,rst)
BEGIN
	if (rst='1') then      
		clk_div <= '0';    
   elsif rising_edge(clk) then
      IF (clk_cnt = "010011100010") THEN
			clk_div <= NOT clk_div;    
      END IF;
   END IF;
END PROCESS;

process(clk_div,rst)
begin
	IF (rst= '1') THEN
      clk_div_cnt <= "0000000000000";    
   ELSIF rising_edge(clk_div) then
      clk_div_cnt <= clk_div_cnt + 1;    
   END IF;
END PROCESS;


PROCESS(clk_div,rst)
BEGIN
	if (rst='1') then
		cs <= IDLE;
   elsif rising_edge(clk_div) then 
      cs <= ns;
	end if;
end process;
		
PROCESS (cs)
begin
	CASE cs IS
		WHEN IDLE =>
			IF (clk_div_cnt = "0001111101000") THEN
				ns <= WR_BYTE;    
         ELSE
				ns <= IDLE;    
         END IF;
      WHEN WR_BYTE =>
         IF (ack = '1') THEN
				ns <= WR_ACK;    
         ELSE
				ns <= WR_BYTE;    
         END IF;
      WHEN WR_ACK =>
         IF (NOT ack = '1') THEN
				ns <= DELAY;    
         ELSE
				ns <= WR_ACK;    
         END IF;
      WHEN DELAY =>
			IF (clk_div_cnt = "0010100010100") THEN
				ns <= RD_BYTE;    
         ELSE
				ns <= DELAY;    
         END IF;
      WHEN RD_BYTE =>
			IF (ack = '1') THEN
				ns <= RD_ACK;    
         ELSE
				ns <= RD_BYTE;    
         END IF;
      WHEN RD_ACK =>
			IF (NOT ack = '1') THEN
				ns <= SHOW;    
         ELSE
				ns <= RD_ACK;    
         END IF;
      WHEN SHOW =>
			IF (show_ok = '1') THEN
				ns <= IDLE;    
			ELSE
				ns <= SHOW;    
			END IF;
      WHEN OTHERS  =>
			ns <= IDLE;          
   END CASE;
END PROCESS;  

PROCESS(clk_div,rst)
BEGIN
	if (rst='1') then      
		wr <= '0';    
      rd <= '0';    
      addr <= "00000000000";    
      data_w <= "00000000";    
      show_ok <= '0';    
      wr_flag <= '0';    
   ELSIF rising_edge(clk_div) then
      IF (data_w = "11111111") THEN
			addr <= "00000000000";    
			data_w <= "00000000";    
      ELSE
         CASE cs IS
				WHEN IDLE =>
					wr <= '0';    
					rd <= '0';    
					show_ok <= '0';    
					wr_flag <= '0';    
				WHEN WR_BYTE =>
					IF (wr_flag = '0') THEN
						wr <= '1';    
						wr_flag <= '1';    
					ELSE
                  wr <= '0';    
               END IF;
            WHEN WR_ACK =>
               wr_flag <= '0';    
            WHEN DELAY =>
               wr <= '0';    
               rd <= '0';    
               show_ok <= '0';    
               wr_flag <= '0';    
            WHEN RD_BYTE =>
               IF (wr_flag = '0') THEN
						rd <= '1';    
                  wr_flag <= '1';    
               ELSE
                  rd <= '0';    
               END IF;
            WHEN RD_ACK =>
               wr_flag <= '0';    
               show_ok <= '1';    
            WHEN SHOW =>
               show_ok <= '0';    
               addr <= addr + "00000000001";    
               data_w <= data_w + "00000001";    
            WHEN OTHERS  =>
               wr <= '0';    
               rd <= '0';    
               show_ok <= '0';    
               wr_flag <= '0';               
         END CASE;
      END IF;
   END IF;
END PROCESS;

PROCESS(clk_div,rst)
BEGIN
	if (rst='1') then    
      data_rep <= "0000000000000000";    
   ELSIF rising_edge(clk_div) then
      IF (show_ok = '1') THEN
			data_rep <= data_w & data_r;    
      END IF;
   END IF;
END PROCESS;

u1:display port map(clk=>clk,data=>data_rep,seg=>seg,sel=>sel);
u2:write port map(clk=>clk_div,rst=>rst,wr=>wr,rd=>rd,addr=>addr,
						data_w=>data_w,data_r=>data_r,ack=>ack,scl=>scl,sda=>sda);


end Behavioral;