tb_fifo.v

来自「一个FIFO的原代码 非常有用 给大家共享了 下吧」· Verilog 代码 · 共 106 行

/********************************************
  A testbench for 8x16 fifo controller.
********************************************/
`timescale 1ns/10ps
module tb_fifo;
  reg clk,rst, rd, wr;
  reg [7:0] datain;
  wire [7:0] dataout;
  wire full, empty;
  
  fifo u1(datain, rd, wr, rst, clk, dataout, full, empty);
  
  initial begin
//    $shm_open("fifo");
//    $shm_probe("AS");
      $dumpfile("fifo.fsdb");
      $dumpvars(0, tb_fifo);
  end
  
  initial begin
    clk=0; rst=0; rd=0; wr=0;
    forever #10 clk = ~clk;
  end
  
  integer i;
  initial begin
    #10;
    rst=1;
// write 16 bytes data in    
    for(i=0;i<16;i=i+1) begin
      @(posedge clk);
      #1;
      wr=1; 
      datain=i+16;
    end
    #20;
    datain=8'h10;
    #20;
    wr=0;
    
    #40;    
// read 16 bytes data out    
    for(i=0;i<16;i=i+1)begin
      @(posedge clk);
      #1;
      rd=1;
    end
    #20;
    rd=0;
    #20;
// write 6 bytes data in
    wr=1;
    #20;
    wr=0;
    
    for(i=0;i<5;i=i+1) begin
      @(posedge clk);
      #1;
      wr=1; 
      datain=i+10;
    end
    #20;
    wr=0;
    #40;
// read more than 6 bytes data out, but empty will be '1' when read 5th byte.    
    for(i=0;i<8;i=i+1)begin
      @(posedge clk);
      #1;
      rd=1;
    end
    #20;
    rd=0;
    #20;    
// write 12 bytes in    
     for(i=0;i<12;i=i+1) begin
      @(posedge clk);
      #1;
      wr=1; 
      datain=i+5;
    end
    #20;
    wr=0;
    #40;   
// read 6 bytes out, and then write data in until fifo is full
    for(i=0;i<6;i=i+1)begin
      @(posedge clk);
      #1;
      rd=1;
    end
    #20;
    rd=0;
    #20;    

     for(i=0;i<16;i=i+1) begin
      @(posedge clk);
      #1;
      wr=1; 
      datain=i;
    end
    #20;
    wr=0;
    #40;   
            
    #100 $stop;
  end
endmodule