2410iic.c

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//参数: slvAddr, addr, *data
//==============================
void Rd24C080(U32 slvAddr,U32 addr,U8 *data)//芯片地址，片内地址，数据
{
    
    _iicMode      = SETRDADDR;//通信模式
    _iicPt        = 0;		  //通信指针
    _iicData[0]   = (U8)addr; //通信数据
    _iicDataCount = 1;		  //通信计数

//IICDS 数据寄存器 [7:0] slvAddr 24c0800芯片的地址
    rIICDS   = slvAddr;

	//IICSTAT Serial output                 [4  ] = 1 : Enable Rx/Tx
    //IICSTAT Busy signal status /START STOP condition
    //                                      [5  ] = 1 : read) Busy (when read) write) START signal generation.
    //IICSTAT Mode selection                [7:6] = 11: Master transmit mode
    rIICSTAT = 0xf0;                    //MasTx,Start  
      //Clearing the pending bit isn't needed because the pending bit has been cleared.

  while(_iicDataCount!=-1);

    _iicMode      = RDDATA;//通信模式
    _iicPt        = 0;	   //通信指针
    _iicDataCount = 1;	   //通信计数
    
    rIICDS        = slvAddr;

	//IICSTAT Serial output                 [4  ] = 1 : Enable Rx/Tx
    //IICSTAT Busy signal status /START STOP condition
    //                                      [5  ] = 1 : read) Busy (when read) write) START signal generation.
    //IICSTAT Mode selection                [7:6] = 10: Master receive mode
    rIICSTAT      = 0xb0;               //MasRx,Start

	//IICCON  Transmit clockvalue        [3:0]  = 1111 : Tx clock = IICCLK/(IICCON[3:0]+1).
	//IICCON  Interrupt pending flag     [4  ]  = 0    : 1) No interrupt pending (when read).
	//													 2) Clear pending condition &
	//													 Resume the operation (when write).
	//IICCON  Tx/Rx Interrupt            [5  ]  = 1    : Enable
	//IICCON  Tx clock source selection  [6  ]  = 0    : IICCLK = fPCLK /16
	//IICCON  Acknowledge generation     [7  ]  = 1    : Enable
	rIICCON       = 0xaf;               //Resumes IIC operation.   
    while(_iicDataCount!=-1);//当数据没有全部传递结束
    *data = _iicData[1];
}


//====================================
//名称： IicInt（）
//功能：中断型IIC通信函数
//返回值:void
//参数: void
//====================================
void __irq IicInt(void)
{
    U32 iicSt,i;
    
    rSRCPND = BIT_IIC;          //Clear pending bit
    rINTPND = BIT_IIC;
    iicSt   = rIICSTAT; 
    
    if(iicSt & 0x8){}           //When bus arbitration is failed.
    if(iicSt & 0x4){}           //When a slave address is matched with IICADD
    if(iicSt & 0x2){}           //When a slave address is 0000000b
    if(iicSt & 0x1){}           //When ACK isn't received

    switch(_iicMode)
    {
       case POLLACK:
           _iicStatus = iicSt;
           break;

       case RDDATA:
           if((_iicDataCount--)==0)
           {
               _iicData[_iicPt++] = rIICDS;

				//IICSTAT Serial output                 [4  ] = 1 : Enable Rx/Tx
                //IICSTAT Busy signal status /START STOP condition
    			//                                      [5  ] = 0 : read) Not busy (when read) 
    			//                                                  write) STOP signal generation
    			//IICSTAT Mode selection                [7:6] = 10: Master receive mode
               rIICSTAT = 0x90;                 //Stop MasRx condition 

				//IICCON  Transmit clockvalue        [3:0]  = 1111 : Tx clock = IICCLK/(IICCON[3:0]+1).
				//IICCON  Interrupt pending flag     [4  ]  = 0    : 1) No interrupt pending (when read).
				//                                                   2) Clear pending condition &
				//														Resume the operation (when write).
				//IICCON  Tx/Rx Interrupt            [5  ]  = 1    : Enable
				//IICCON  Tx clock source selection  [6  ]  = 0    : IICCLK = fPCLK /16
				//IICCON  Acknowledge generation     [7  ]  = 1    : Enable
			   rIICCON  = 0xaf;                 //Resumes IIC operation.
               Delay(1);                        //Wait until stop condtion is in effect.
                                                //Too long time... 
                                                //The pending bit will not be set after issuing stop condition.
               break;    
           }      
           _iicData[_iicPt++] = rIICDS;         //The last data has to be read with no ack.

           if((_iicDataCount)==0)

		   	    //IICCON  Transmit clockvalue        [3:0]  = 1111 : Tx clock = IICCLK/(IICCON[3:0]+1).
				//IICCON  Interrupt pending flag     [4  ]  = 0    : 1) No interrupt pending (when read).
				//                                                   2) Clear pending condition &
				//														Resume the operation (when write).
				//IICCON  Tx/Rx Interrupt            [5  ]  = 1    : Enable
				//IICCON  Tx clock source selection  [6  ]  = 0    : IICCLK = fPCLK /16
				//IICCON  Acknowledge generation     [7  ]  = 0    : disable
               rIICCON = 0x2f;                  //Resumes IIC operation with NOACK.  
           else 
		   		//IICCON  Transmit clockvalue        [3:0]  = 1111 : Tx clock = IICCLK/(IICCON[3:0]+1).
				//IICCON  Interrupt pending flag     [4  ]  = 0    : 1) No interrupt pending (when read).
				//                                                   2) Clear pending condition &
				//														Resume the operation (when write).
				//IICCON  Tx/Rx Interrupt            [5  ]  = 1    : Enable
				//IICCON  Tx clock source selection  [6  ]  = 0    : IICCLK = fPCLK /16
				//IICCON  Acknowledge generation     [7  ]  = 1    : Enable
			   rIICCON = 0xaf;                  //Resumes IIC operation with ACK
               break;

        case WRDATA:
            if((_iicDataCount--)==0)
            {
            	//IICSTAT Last-received bit status flag [0  ] = 0 : Last-received bit is 0 (ACK was received).
				//IICSTAT Address zero status flag      [1  ] = 0 : Cleared when START/STOP condition was detected.
			    //IICSTAT Address-as-slavestatus flag   [2  ] = 0 : Cleared when START/STOP condition was detected
			    //IICSTAT Arbitration status flag       [3  ] = 0 : Bus arbitration successful
            	//IICSTAT Serial output                 [4  ] = 1 : Enable Rx/Tx
                //IICSTAT Busy signal status /START STOP condition
    			//                                      [5  ] = 0 : read) Not busy (when read) 
    			//                                                  write) STOP signal generation
    			//IICSTAT Mode selection                
                rIICSTAT = 0xd0;                //Stop MasTx condition 

		   		//IICCON  Transmit clockvalue        [3:0]  = 1111 : Tx clock = IICCLK/(IICCON[3:0]+1).
				//IICCON  Interrupt pending flag     [4  ]  = 0    : 1) No interrupt pending (when read).
				//                                                   2) Clear pending condition &
				//														Resume the operation (when write).
				//IICCON  Tx/Rx Interrupt            [5  ]  = 1    : Enable
				//IICCON  Tx clock source selection  [6  ]  = 0    : IICCLK = fPCLK /16
				//IICCON  Acknowledge generation     [7  ]  = 1    : Enable
			    rIICCON  = 0xaf;                //Resumes IIC operation.
                Delay(1);                       //Wait until stop condtion is in effect.
                       //The pending bit will not be set after issuing stop condition.
                break;    
            }
            rIICDS = _iicData[_iicPt++];        //_iicData[0] has dummy.
            for(i=0;i<10;i++);                  //for setup time until rising edge of IICSCL

		   		//IICCON  Transmit clockvalue        [3:0]  = 1111 : Tx clock = IICCLK/(IICCON[3:0]+1).
				//IICCON  Interrupt pending flag     [4  ]  = 0    : 1) No interrupt pending (when read).
				//                                                   2) Clear pending condition &
				//														Resume the operation (when write).
				//IICCON  Tx/Rx Interrupt            [5  ]  = 1    : Enable
				//IICCON  Tx clock source selection  [6  ]  = 0    : IICCLK = fPCLK /16
				//IICCON  Acknowledge generation     [7  ]  = 1    : Enable              
                rIICCON = 0xaf;                     //resumes IIC operation.
                break;

        case SETRDADDR:
//            Uart_Printf("__irq IicInt SETDADDR [ S%d ]",_iicDataCount);
            if((_iicDataCount--)==0)
                break;                          //IIC operation is stopped because of IICCON[4]    
            rIICDS = _iicData[_iicPt++];
            for(i=0;i<10;i++);                  //For setup time until rising edge of IICSCL
		   		//IICCON  Transmit clockvalue        [3:0]  = 1111 : Tx clock = IICCLK/(IICCON[3:0]+1).
				//IICCON  Interrupt pending flag     [4  ]  = 0    : 1) No interrupt pending (when read).
				//                                                   2) Clear pending condition &
				//														Resume the operation (when write).
				//IICCON  Tx/Rx Interrupt            [5  ]  = 1    : Enable
				//IICCON  Tx clock source selection  [6  ]  = 0    : IICCLK = fPCLK /16
				//IICCON  Acknowledge generation     [7  ]  = 1    : Enable
			rIICCON = 0xaf;                     //Resumes IIC operation.
            break;
        default:
            break;      
    }
}