sdi.c

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    ClearPending(BIT_SDI);
}

void __irq Wt_Int(void)
{
    ClearPending(BIT_SDI);

	//SDIDAT Data Register [31:0]  This field contains the data to be transmitted or received over the SDI channel.
    rSDIDAT=*Tx_buffer++;
    wt_cnt++;

    if(wt_cnt==128*block)
    {
	//INTMSK  INT_SDI [21] = 1 : Masked
	rINTMSK |= BIT_SDI; 
	//SDIDAT Data Register [31:0]  This field contains the data to be transmitted or received over the SDI channel
	rSDIDAT=*Tx_buffer;
	TR_end=1;
    }
}

void __irq DMA_end(void)
{
    ClearPending(BIT_DMA0);
    
    TR_end=1;
}
/*****************************************
  读存储块函数
  函数名: Rd_Block
  描述: 通过三种方式读存储块
  返回值：void
*****************************************/

void Rd_Block(void)
{
    U32 mode;
    int status;

    rd_cnt=0;    
    Uart_Printf("[Block read test]\n");

RE0:
    Uart_Printf("0:Polling read   1:Interrupt read   2:DMA read\nSelect the test mode?");
    mode=(U32)Uart_GetIntNum();
    Uart_Printf("\n");

    if(mode>2)
	goto RE0;

	//SDICON FIFO Reset (FRST) [1] = 1 : FIFO reset
    rSDICON |= rSDICON|(1<<1);	
    
	//    mode=2;//tark
    if(mode!=2)
    
	//SDIDCON  BlkNum                           [11: 0] = block : Block Number (0~4095).
    //SDIDCON  Data Transfer Mode (DatMode)     [13:12] = 2     : Rx start
    //SDIDCON  Stop by force (STOP)             [14   ] = 0     : normal
    //SDIDCON  DMA Enable(EnDMA)			    [15   ] = 0     : disable(polling),
    //SDIDCON  Wide bus enable (WideBus)        [16   ] = Wide  : 4bit bus
    //SDIDCON  Block mode (BlkMode)  		    [17   ] = 1     : blk 
    //SDIDCON  Busy AfterCommand(BACMD)         [18   ] = 0     : directly after DatMode set,
    //SDIDCON  Receive After Command (RACMD)    [19   ] = 1     : Rx after cmd
    //SDIDCON  Transmit After Response(TARSP)   [20   ] = 0     : directly after DatMode set,
    //SDIDCON  SDIO InterruptPeriodType(PrdType)[21   ] = 0     : exactly 2 cycle,
	rSDIDCON=(1<<19)|(1<<17)|(Wide<<16)|(2<<12)|(block<<0);
	
	//SDICARG  CmdArg  [31:0] = 0 :  CMD17/18(addr)
    rSDICARG=0x0;

RERDCMD:
    switch(mode)
    {
	case POL:
	    if(block<2)	// SINGLE_READ
	    {
		//SDICCON CmdIndex              [7:0] = 0X51 : CMD17
	    //SDICCON Command Start(CMST)   [8  ] = 1    : command start
	    //SDICCON WaitRsp               [9  ] = 1    : wait_resp
	    //SDICCON LongRsp               [10 ] = 0    : short response
	  	rSDICCON=(0x1<<9)|(0x1<<8)|0x51;  
		
		if(!Chk_CMDend(17, 1))	//-- Check end of CMD17
		    goto RERDCMD;	    
	    }
	    else	// MULTI_READ
	    {
	    //SDICCON CmdIndex              [7:0] = 0X52 : CMD18
	    //SDICCON Command Start(CMST)   [8  ] = 1    : command start
	    //SDICCON WaitRsp               [9  ] = 1    : wait_resp
	    //SDICCON LongRsp               [10 ] = 0    : short response
	  	rSDICCON=(0x1<<9)|(0x1<<8)|0x52;    // sht_resp, wait_resp, dat, start, CMD18
		if(!Chk_CMDend(18, 1))	//-- Check end of CMD18 
		    goto RERDCMD;
	    }

	    //rSDICSTA=0xa00;	// Clear cmd_end(with rsp)	    

	    while(rd_cnt<128*block)	// 512*block bytes
	    {
		if((rSDIDSTA&0x20)==0x20) // Check timeout 
		{
		    //SDIDSTA  Data Time Out (DatTout) [5] = 1 : timeout
		    rSDIDSTA=0x1<<0x5; 
		    break;
		}
		status=rSDIFSTA;
		if((status&0x1000)==0x1000)	// Is Rx data?
		{
		    *Rx_buffer++=rSDIDAT;
		    rd_cnt++;
		}
	    }
	    break;
	
	case INT:
	    pISR_SDI=(unsigned)Rd_Int;
	    
	    //INTMSK  INT_SDI [21] = 0 : service available,
	    rINTMSK = ~(BIT_SDI);
	    
	    //SDIIMSK  RFHalf Interrupt Enable [0] = 1 : interrupt enable
	    //SDIIMSK  RFLast Interrupt Enable [2] = 1 : interrupt enable
	    rSDIIMSK=5;

	    if(block<2)	// SINGLE_READ
	    {
	    //SDICCON CmdIndex              [7:0] = 0X51 : CMD17
	    //SDICCON Command Start(CMST)   [8  ] = 1    : command start
	    //SDICCON WaitRsp               [9  ] = 1    : wait_resp
	    //SDICCON LongRsp               [10 ] = 0    : short response
		rSDICCON=(0x1<<9)|(0x1<<8)|0x51;   
		if(!Chk_CMDend(17, 1))	//-- Check end of CMD17
		    goto RERDCMD;	    
	    }
	    else	// MULTI_READ
	    {
		//SDICCON CmdIndex              [7:0] = 0X52 : CMD18
	    //SDICCON Command Start(CMST)   [8  ] = 1    : command start
	    //SDICCON WaitRsp               [9  ] = 1    : wait_resp
	    //SDICCON LongRsp               [10 ] = 0    : short response
		rSDICCON=(0x1<<9)|(0x1<<8)|0x52;    // sht_resp, wait_resp, dat, start, CMD18
		if(!Chk_CMDend(18, 1))	//-- Check end of CMD18 
		    goto RERDCMD;
	    }
    
	    //rSDICSTA=0xa00;	// Clear cmd_end(with rsp)

	    while(rd_cnt<128*block);
		
		//INTMSK  INT_SDI [21] = 1 : Masked
	    rINTMSK |= (BIT_SDI);
	    //SDIIMSK  SDI interrupt mask register [17: 0] = 0 : All mask
	    rSDIIMSK=0;	
	     break;

	case DMA:
	    pISR_DMA0=(unsigned)DMA_end;
	    //INTMSK INT_DMA0  [17] = 0 : Service availa
	    rINTMSK = ~(BIT_DMA0);

		//DISRC0  S_ADDR  [30:0] = SDIDAT : SDIDAT
	    rDISRC0=(int)(SDIDAT);	// SDIDAT
	    
	    //DISRCC0 INC [0] = 1 : Fixed
	    //DISRCC0 LOC [1] = 1 : the source is in the peripheral bus (APB).
	    rDISRCC0=(1<<1)+(1<<0);	
	    
	    rDIDST0=(U32)(Rx_buffer);	// Rx_buffer
	    
	    //DIDSTC0 INC [0] = 0 : Increment
	    //DIDSTC0 LOC [1] = 0 : AHB
	    rDIDSTC0=(0<<1)+(0<<0);	// AHB, inc
	   
	    //DCON0 TC          [19: 0] = 10000000 : Initial transfer count (or transfer beat).
	    //DCON0 DSZ 		[21:20] = 10	   : Word
	    //DCON0 RELOAD      [22   ] = 1        : auto-reload of
	    //DCON0 SWHW_SEL    [23   ] = 1        : H/W request
	    //DCON0 HWSRCSEL    [26:24] = 10       : SDI
	    //DCON0 SERVMODE    [27   ] = 0        : single service
	    //DCON0 TSZ         [28   ] = 0        : single tx
	    //DCON0 INT         [29   ] = 1		   : TC int
	    //DCON0 SYNC        [30   ] = 0        : sync PCLK
	    //DCON0 DMD_HS      [31   ] = 1        : handshake
	    rDCON0=(1<<31)+(0<<30)+(1<<29)+(0<<28)+(0<<27)+(2<<24)+(1<<23)+(1<<22)+(2<<20)+128*block;
	    
	    //DMASKTRIG0  SW_TRIG [0] = 0 : no-sw trigger 
	    //DMASKTRIG0  ON_OFF  [1] = 1 : DMA2 channel on
	    //DMASKTRIG0  STOP    [2] = 0 : no-stop
	    rDMASKTRIG0=(0<<2)+(1<<1)+0;   

		//SDIDCON  BlkNum                           [11: 0] = block : Block Number (0~4095).
	    //SDIDCON  Data Transfer Mode (DatMode)     [13:12] = 2     : Rx start
	    //SDIDCON  Stop by force (STOP)             [14   ] = 0     : normal
	    //SDIDCON  DMA Enable(EnDMA)			    [15   ] = 1     : dma enable,
	    //SDIDCON  Wide bus enable (WideBus)        [16   ] = Wide  : 4bit bus
	    //SDIDCON  Block mode (BlkMode)  		    [17   ] = 1     : blk 
	    //SDIDCON  Busy AfterCommand(BACMD)         [18   ] = 0     : directly after DatMode set,
	    //SDIDCON  Receive After Command (RACMD)    [19   ] = 1     : Rx after cmd
	    //SDIDCON  Transmit After Response(TARSP)   [20   ] = 0     : directly after DatMode set,
	    //SDIDCON  SDIO InterruptPeriodType(PrdType)[21   ] = 0     : exactly 2 cycle,
		rSDIDCON=(1<<19)|(1<<17)|(Wide<<16)|(1<<15)|(2<<12)|(block<<0);
		    // Rx after rsp, blk, 4bit bus, dma enable, Rx start, blk num
	    if(block<2)	// SINGLE_READ
	    {
	   	//SDICCON CmdIndex              [7:0] = 0X51 : CMD17
	    //SDICCON Command Start(CMST)   [8  ] = 1    : command start
	    //SDICCON WaitRsp               [9  ] = 1    : wait_resp
	    //SDICCON LongRsp               [10 ] = 0    : short response
		rSDICCON=(0x1<<9)|(0x1<<8)|0x51;    // sht_resp, wait_resp, dat, start, CMD17
		if(!Chk_CMDend(17, 1))	//-- Check end of CMD17
		    goto RERDCMD;	    
	    }
	    else	// MULTI_READ
	    {
		//SDICCON CmdIndex              [7:0] = 0X52 : CMD18
	    //SDICCON Command Start(CMST)   [8  ] = 1    : command start
	    //SDICCON WaitRsp               [9  ] = 1    : wait_resp
	    //SDICCON LongRsp               [10 ] = 0    : short response
		rSDICCON=(0x1<<9)|(0x1<<8)|0x52;    // sht_resp, wait_resp, dat, start, CMD18
		if(!Chk_CMDend(18, 1))	//-- Check end of CMD18 
		    goto RERDCMD;
	    }

	    //rSDICSTA=0xa00;	// Clear cmd_end(with rsp)
	    while(!TR_end);
		//Uart_Printf("rSDIFSTA=0x%x\n",rSDIFSTA);
	    
	    //INTMSK  BIT_DMA0 [17] = 1 : MASK
	    rINTMSK |= (BIT_DMA0);
		TR_end=0;

		//DMASKTRIG0  STOP [2] = 1 : DMA0 stop
		rDMASKTRIG0=(1<<2);	
	    break;

	default:
	    break;
    }
    //-- Check end of DATA
    if(!Chk_DATend()) 
	Uart_Printf("dat error\n");

	//SDIDSTA  Rx Data Progress On (RxDatOn) [0 ]  R  : Data receive in progress.
	//SDIDSTA  Tx Data progress On (TxDatOn) [1 ]  R  : Data transmit in progress.
	//SDIDSTA  Start Bit Error (SbitErr)     [2 ] =0  : not detect,
	//SDIDSTA  Busy Finish (BusyFin)         [3 ] =0  : not detect,
	//SDIDSTA  Data Transfer Finish (DatFin) [4 ] =1  : data finish detect
	//SDIDSTA  Data Time Out (DatTout)       [5 ] =0  : not detect,
	//SDIDSTA  Data Receive CRC Fail (DatCrc)[6 ] =0  : not detect,
	//SDIDSTA  CRC Status Fail(CrcSta)       [7 ] =0  : not detect,
	//SDIDSTA  FIFO Fail error (FFfail)      [8 ] =0  : not detect,
	//SDIDSTA  SDIO InterruptDetect(IOIntDet)[9 ] =0  : not detect,
	//SDIDSTA  Data Time Out (DatTout)       [10] =0  : not occur,
    rSDIDSTA=0x10;	// Clear data Tx/Rx end

    if(block>1)
    {
RERCMD12:    
	//--Stop cmd(CMD12)
	//SDICARG CmdArg [31:0] = 0 : Command Argument
	rSDICARG=0x0;	    //CMD12(stuff bit)

	//SDICCON CmdIndex              [7:0] = 0X4C : CMD12
	//SDICCON Command Start(CMST)   [8  ] = 1    : command start
	//SDICCON WaitRsp               [9  ] = 1    : wait_resp
	//SDICCON LongRsp               [10 ] = 0    : short response
	rSDICCON=(0x1<<9)|(0x1<<8)|0x4c;

	//-- Check end of CMD12
	if(!Chk_CMDend(12, 1)) 
	    goto RERCMD12;
	//rSDICSTA=0xa00;	// Clear cmd_end(with rsp)
    }
}


void Rd_Stream(void)	// only for MMC, 3blk read
{
    int i;
    int status, rd_cnt=0;

    if(MMC!=1)
    {
	Uart_Printf("Stream read command supports only MMC!\n");
	return;
    }    
    Uart_Printf("\n[Stream read test]\n");
    
RECMD11:
	//SDIDCON  BlkNum                           [11: 0] = block : Block Number (0~4095).
	//SDIDCON  Data Transfer Mode (DatMode)     [13:12] = 2     : Rx start
	//SDIDCON  Stop by force (STOP)             [14   ] = 0     : normal
	//SDIDCON  DMA Enable(EnDMA)			    [15   ] = 1     : dma enable,
	//SDIDCON  Wide bus enable (WideBus)        [16   ] = 0     : standard bus mode(only SDIDAT[0] used),
	//SDIDCON  Block mode (BlkMode)  		    [17   ] = 0     : stream data transfer,
	//SDIDCON  Busy AfterCommand(BACMD)         [18   ] = 0     : directly after DatMode set,
	//SDIDCON  Receive After Command (RACMD)    [19   ] = 1     : Rx after cmd
	//SDIDCON  Transmit After Response(TARSP)   [20   ] = 0     : directly after DatMode set,
	//SDIDCON  SDIO InterruptPeriodType(PrdType)[21   ] = 0     : exactly 2 cycle,
	rSDIDCON=(1<<19)|(0<<17)|(0<<16)|(2<<12);

	//SDICARG CmdArg [31:0] = 0 : Command Argument
    rSDICARG=0x0;   // CMD11(addr)

	//SDICCON CmdIndex              [7:0] = 0X4B : CMD11
	//SDICCON Command Start(CMST)   [8  ] = 1    : command start
	//SDICCON WaitRsp               [9  ] = 1    : wait_resp
	//SDICCON LongRsp               [10 ] = 0    : short response
	rSDICCON=(0x1<<9)|(0x1<<8)|0x4b;   //sht_resp, wait_resp, dat, start, CMD11

    while(rd_cnt<128*block)
    {
	if( (rSDIDSTA&0x20) == 0x20 )
	{
	    Uart_Printf("Rread timeout error");
	    return ;
	}
	    
	status=rSDIFSTA;
	if((status&0x1000)==0x1000)
	{
	    //*Rx_buffer++=rSDIDAT;
	    //rd_cnt++;
	    Rx_buffer[rd_cnt++]=rSDIDAT;
	}
    }

    //-- Check end of CMD11
    if(!Chk_CMDend(11, 1)) 
	goto RECMD11;
    //rSDICSTA=0xa00;	// Clear cmd_end(with rsp)

    //-- Check end of DATA
	//SDIDCON  BlkNum                           [11: 0] = block : Block Number (0~4095).
	//SDIDCON  Data Transfer Mode (DatMode)     [13:12] = 0     : ready,
	//SDIDCON  Stop by force (STOP)             [14   ] = 1     : stop by force
	//SDIDCON  DMA Enable(EnDMA)			    [15   ] = 1     : dma enable,
	//SDIDCON  Wide bus enable (WideBus)        [16   ] = 0     : standard bus mode(only SDIDAT[0] used),
	//SDIDCON  Block mode (BlkMode)  		    [17   ] = 0     : stream data transfer,
	//SDIDCON  Busy AfterCommand(BACMD)         [18   ] = 0     : directly after DatMode set,
	//SDIDCON  Receive After Command (RACMD)    [19   ] = 1     : Rx after cmd
	//SDIDCON  Transmit After Response(TARSP)   [20   ] = 0     : directly after DatMode set,
	//SDIDCON  SDIO InterruptPeriodType(PrdType)[21   ] = 0     : exactly 2 cycle,
	rSDIDCON=(1<<19)|(0<<17)|(0<<16)|(1<<14)|(0<<12);
    while( rSDIDSTA&0x3 !=0x0 );
    if(rSDIDSTA!=0) 
	Uart_Printf("rSDIDSTA=0x%x\n", rSDIDSTA);
	//SDIDSTA  Rx Data Progress On (RxDatOn) [0 ]  R  : Data receive in progress.
	//SDIDSTA  Tx Data progress On (TxDatOn) [1 ]  R  : Data transmit in progress.
	//SDIDSTA  Start Bit Error (SbitErr)     [2 ] =1  : command end
	//SDIDSTA  Busy Finish (BusyFin)         [3 ] =1  : busy finish detect
	//SDIDSTA  Data Transfer Finish (DatFin) [4 ] =1  : data finish detect
	//SDIDSTA  Data Time Out (DatTout)       [5 ] =1  : timeout
	//SDIDSTA  Data Receive CRC Fail (DatCrc)[6 ] =1  : receive crc fail
	//SDIDSTA  CRC Status Fail(CrcSta)       [7 ] =1  : crc status fail
	//SDIDSTA  FIFO Fail error (FFfail)      [8 ] =0  : not detect,
	//SDIDSTA  SDIO InterruptDetect(IOIntDet)[9 ] =0  : not detect,
	//SDIDSTA  Data Time Out (DatTout)       [10] =0  : not occur,
	rSDIDSTA=0xff;

STRCMD12:    
    //--Stop cmd(CMD12)
	//SDICARG CmdArg [31:0] = 0 : Command Argument
	rSDICARG=0x0;	    //CMD12(stuff bit)