1368_1.rpt

用pci9052开发pci板卡的全套资料,含有原理图封装,和eeprom文件1

21   -> - - - - - - - - - - - - - - * | - - - * | <-- LHOLDA
88   -> - - - - - - - - - - - - - - - | - - * - | <-- /WR
87   -> - - - - - - - - - - - - - - - | - - - - | <-- 32MHZ


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                   c:\mev\live\1368\pld\1368_1.rpt
1368_1

** EQUATIONS **

ALE      : INPUT;
IRQ2/9   : INPUT;
IRQ3     : INPUT;
IRQ4     : INPUT;
IRQ5     : INPUT;
IRQ6     : INPUT;
IRQ7     : INPUT;
IRQ10    : INPUT;
IRQ11    : INPUT;
IRQ12    : INPUT;
IRQ14    : INPUT;
IRQ15    : INPUT;
LA20     : INPUT;
LA21     : INPUT;
LA22     : INPUT;
LA23     : INPUT;
LCLK     : INPUT;
LHOLD    : INPUT;
LHOLDA   : INPUT;
32MHZ    : INPUT;
/CSRAM   : INPUT;
/CSROM   : INPUT;
/CS0     : INPUT;
/CS1     : INPUT;
/LBE0    : INPUT;
/LBE1    : INPUT;
/LBE2    : INPUT;
/LBE3    : INPUT;
/NOWSI   : INPUT;
/WR      : INPUT;
/XCSRAM  : INPUT;
/XCSROM  : INPUT;

-- Node name is 'ISA_INT' 
-- Equation name is 'ISA_INT', location is LC044, type is output.
 ISA_INT = LCELL( _EQ001 $  VCC);
  _EQ001 = !IRQ2/9 & !IRQ3 & !IRQ4 & !IRQ5 & !IRQ6 & !IRQ7 & !IRQ10 & !IRQ11 & 
             !IRQ12 & !IRQ14 & !IRQ15;

-- Node name is 'PC1' 
-- Equation name is 'PC1', location is LC024, type is output.
 PC1     = LCELL( GND $  GND);

-- Node name is 'PC8' 
-- Equation name is 'PC8', location is LC049, type is output.
 PC8     = LCELL( GND $  GND);

-- Node name is 'PC9' 
-- Equation name is 'PC9', location is LC050, type is output.
 PC9     = LCELL( GND $  GND);

-- Node name is 'PC10' 
-- Equation name is 'PC10', location is LC052, type is output.
 PC10    = LCELL( GND $  GND);

-- Node name is 'PC11' 
-- Equation name is 'PC11', location is LC053, type is output.
 PC11    = LCELL( GND $  GND);

-- Node name is 'PC12' 
-- Equation name is 'PC12', location is LC054, type is output.
 PC12    = LCELL( GND $  GND);

-- Node name is 'PC13' 
-- Equation name is 'PC13', location is LC055, type is output.
 PC13    = LCELL( GND $  GND);

-- Node name is 'PC14' 
-- Equation name is 'PC14', location is LC057, type is output.
 PC14    = LCELL( GND $  GND);

-- Node name is 'PC15' 
-- Equation name is 'PC15', location is LC058, type is output.
 PC15    = LCELL( GND $  GND);

-- Node name is 'PC16' 
-- Equation name is 'PC16', location is LC059, type is output.
 PC16    = LCELL( GND $  GND);

-- Node name is 'PC17' 
-- Equation name is 'PC17', location is LC060, type is output.
 PC17    = LCELL( GND $  GND);

-- Node name is 'PC18' 
-- Equation name is 'PC18', location is LC061, type is output.
 PC18    = LCELL( GND $  GND);

-- Node name is 'PC19' 
-- Equation name is 'PC19', location is LC062, type is output.
 PC19    = LCELL( GND $  GND);

-- Node name is 'PC20' 
-- Equation name is 'PC20', location is LC063, type is output.
 PC20    = LCELL( GND $  GND);

-- Node name is 'PC21' 
-- Equation name is 'PC21', location is LC064, type is output.
 PC21    = LCELL( GND $  GND);

-- Node name is '8MHZ' = '|9052rdfif:169|8MHZ' 
-- Equation name is '8MHZ', type is output 
 8MHZ    = TFFE( 16MHZ, GLOBAL( 32MHZ),  VCC,  VCC,  VCC);

-- Node name is '16MHZ' = '|9052rdfif:169|16MHZ' 
-- Equation name is '16MHZ', type is output 
 16MHZ   = TFFE( VCC, GLOBAL( 32MHZ),  VCC,  VCC,  VCC);

-- Node name is '|9052rdfif:169|:55' = '|9052rdfif:169|LMASTER' 
-- Equation name is '_LC051', type is buried 
_LC051   = DFFE( LHOLD $  GND,  LHOLDA,  LHOLD,  VCC,  VCC);

-- Node name is '/CSROMO' 
-- Equation name is '/CSROMO', location is LC022, type is output.
 /CSROMO = LCELL( _EQ002 $  VCC);
  _EQ002 =  _LC051 & !/XCSROM
         # !/CSROM & !_LC051;

-- Node name is '/NOWSO' = '|9052rdfif:169|/NOWSO' 
-- Equation name is '/NOWSO', type is output 
 /NOWSO  = DFFE( /NOWSI $  GND, GLOBAL( LCLK),  VCC, !ALE,  VCC);

-- Node name is '/RCS0' 
-- Equation name is '/RCS0', location is LC016, type is output.
 /RCS0   = LCELL( _EQ003 $  VCC);
  _EQ003 = !/LBE0 &  _LC051 & !/XCSRAM
         # !/CSRAM & !/LBE0 & !_LC051;

-- Node name is '/RCS1' 
-- Equation name is '/RCS1', location is LC015, type is output.
 /RCS1   = LCELL( _EQ004 $  VCC);
  _EQ004 = !/LBE1 &  _LC051 & !/XCSRAM
         # !/CSRAM & !/LBE1 & !_LC051;

-- Node name is '/RCS2' 
-- Equation name is '/RCS2', location is LC014, type is output.
 /RCS2   = LCELL( _EQ005 $  VCC);
  _EQ005 = !/LBE2 &  _LC051 & !/XCSRAM
         # !/CSRAM & !/LBE2 & !_LC051;

-- Node name is '/RCS3' 
-- Equation name is '/RCS3', location is LC013, type is output.
 /RCS3   = LCELL( _EQ006 $  VCC);
  _EQ006 = !/LBE3 &  _LC051 & !/XCSRAM
         # !/CSRAM & !/LBE3 & !_LC051;

-- Node name is '/RWE' 
-- Equation name is '/RWE', location is LC047, type is output.
 /RWE    = LCELL( _EQ007 $  VCC);
  _EQ007 = !LCLK & !/WR;

-- Node name is '/SMEMR' 
-- Equation name is '/SMEMR', location is LC045, type is output.
 /SMEMR  = LCELL( _EQ008 $  VCC);
  _EQ008 = !/CS0 & !LA20 & !LA21 & !LA22 & !LA23;

-- Node name is '/SMEMW' 
-- Equation name is '/SMEMW', location is LC046, type is output.
 /SMEMW  = LCELL( _EQ009 $  VCC);
  _EQ009 = !/CS1 & !LA20 & !LA21 & !LA22 & !LA23;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                            c:\mev\live\1368\pld\1368_1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX3000A' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = off
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:03
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 9,617K