📄 1368_1.rpt
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Total shareable expanders in database: 0
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: c:\mev\live\1368\pld\1368_1.rpt
1368_1
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
25 (25) (B) INPUT 0 0 0 0 0 1 0 ALE
12 (3) (A) INPUT 0 0 0 0 0 4 0 /CSRAM
30 (23) (B) INPUT 0 0 0 0 0 1 0 /CSROM
13 (2) (A) INPUT 0 0 0 0 0 1 0 /CS0
14 (1) (A) INPUT 0 0 0 0 0 1 0 /CS1
40 (33) (C) INPUT 0 0 0 0 0 1 0 IRQ2/9
41 (34) (C) INPUT 0 0 0 0 0 1 0 IRQ3
42 (35) (C) INPUT 0 0 0 0 0 1 0 IRQ4
44 (36) (C) INPUT 0 0 0 0 0 1 0 IRQ5
45 (37) (C) INPUT 0 0 0 0 0 1 0 IRQ6
46 (38) (C) INPUT 0 0 0 0 0 1 0 IRQ7
47 (39) (C) INPUT 0 0 0 0 0 1 0 IRQ10
48 (40) (C) INPUT 0 0 0 0 0 1 0 IRQ11
52 (41) (C) INPUT 0 0 0 0 0 1 0 IRQ12
54 (42) (C) INPUT 0 0 0 0 0 1 0 IRQ14
56 (43) (C) INPUT 0 0 0 0 0 1 0 IRQ15
16 (31) (B) INPUT 0 0 0 0 0 2 0 LA20
17 (30) (B) INPUT 0 0 0 0 0 2 0 LA21
19 (29) (B) INPUT 0 0 0 0 0 2 0 LA22
20 (28) (B) INPUT 0 0 0 0 0 2 0 LA23
6 (7) (A) INPUT 0 0 0 0 0 1 0 /LBE0
8 (6) (A) INPUT 0 0 0 0 0 1 0 /LBE1
9 (5) (A) INPUT 0 0 0 0 0 1 0 /LBE2
10 (4) (A) INPUT 0 0 0 0 0 1 0 /LBE3
90 - - INPUT G 0 0 0 0 0 1 0 LCLK
23 (26) (B) INPUT 0 0 0 0 0 0 1 LHOLD
21 (27) (B) INPUT 0 0 0 0 0 0 1 LHOLDA
32 (21) (B) INPUT 0 0 0 0 0 1 0 /NOWSI
88 - - INPUT 0 0 0 0 0 1 0 /WR
36 (18) (B) INPUT 0 0 0 0 0 4 0 /XCSRAM
37 (17) (B) INPUT 0 0 0 0 0 1 0 /XCSROM
87 - - INPUT G 0 0 0 0 0 0 0 32MHZ
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\mev\live\1368\pld\1368_1.rpt
1368_1
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
31 22 B OUTPUT t 0 0 0 2 1 0 0 /CSROMO
57 44 C OUTPUT t 0 0 0 11 0 0 0 ISA_INT
35 19 B FF + t 0 0 0 2 0 0 0 /NOWSO (|9052rdfif:169|:73)
29 24 B OUTPUT t 0 0 0 0 0 0 0 PC1
63 49 D OUTPUT t 0 0 0 0 0 0 0 PC8
64 50 D OUTPUT t 0 0 0 0 0 0 0 PC9
67 52 D OUTPUT t 0 0 0 0 0 0 0 PC10
68 53 D OUTPUT t 0 0 0 0 0 0 0 PC11
69 54 D OUTPUT t 0 0 0 0 0 0 0 PC12
71 55 D OUTPUT t 0 0 0 0 0 0 0 PC13
75 57 D OUTPUT t 0 0 0 0 0 0 0 PC14
76 58 D OUTPUT t 0 0 0 0 0 0 0 PC15
79 59 D OUTPUT t 0 0 0 0 0 0 0 PC16
80 60 D OUTPUT t 0 0 0 0 0 0 0 PC17
81 61 D OUTPUT t 0 0 0 0 0 0 0 PC18
83 62 D OUTPUT t 0 0 0 0 0 0 0 PC19
84 63 D OUTPUT t 0 0 0 0 0 0 0 PC20
85 64 D OUTPUT t 0 0 0 0 0 0 0 PC21
92 16 A OUTPUT t 0 0 0 3 1 0 0 /RCS0
93 15 A OUTPUT t 0 0 0 3 1 0 0 /RCS1
94 14 A OUTPUT t 0 0 0 3 1 0 0 /RCS2
96 13 A OUTPUT t 0 0 0 3 1 0 0 /RCS3
61 47 C OUTPUT t 0 0 0 2 0 0 0 /RWE
58 45 C OUTPUT t 0 0 0 5 0 0 0 /SMEMR
60 46 C OUTPUT t 0 0 0 5 0 0 0 /SMEMW
99 10 A FF + t 0 0 0 0 1 0 0 8MHZ (|9052rdfif:169|:12)
100 9 A FF + t 0 0 0 0 0 1 0 16MHZ (|9052rdfif:169|:11)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\mev\live\1368\pld\1368_1.rpt
1368_1
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 51 D DFFE t 0 0 0 2 0 5 0 |9052rdfif:169|LMASTER (|9052rdfif:169|:55)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\mev\live\1368\pld\1368_1.rpt
1368_1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----------- LC16 /RCS0
| +--------- LC15 /RCS1
| | +------- LC14 /RCS2
| | | +----- LC13 /RCS3
| | | | +--- LC10 8MHZ
| | | | | +- LC9 16MHZ
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'A'
LC | | | | | | | A B C D | Logic cells that feed LAB 'A':
LC9 -> - - - - * * | * - - - | <-- 16MHZ
Pin
12 -> * * * * - - | * - - - | <-- /CSRAM
6 -> * - - - - - | * - - - | <-- /LBE0
8 -> - * - - - - | * - - - | <-- /LBE1
9 -> - - * - - - | * - - - | <-- /LBE2
10 -> - - - * - - | * - - - | <-- /LBE3
90 -> - - - - - - | - - * - | <-- LCLK
88 -> - - - - - - | - - * - | <-- /WR
36 -> * * * * - - | * - - - | <-- /XCSRAM
87 -> - - - - - - | - - - - | <-- 32MHZ
LC51 -> * * * * - - | * * - - | <-- |9052rdfif:169|LMASTER
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\mev\live\1368\pld\1368_1.rpt
1368_1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----- LC22 /CSROMO
| +--- LC19 /NOWSO
| | +- LC24 PC1
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'B'
LC | | | | A B C D | Logic cells that feed LAB 'B':
Pin
25 -> - * - | - * - - | <-- ALE
30 -> * - - | - * - - | <-- /CSROM
90 -> - - - | - - * - | <-- LCLK
32 -> - * - | - * - - | <-- /NOWSI
88 -> - - - | - - * - | <-- /WR
37 -> * - - | - * - - | <-- /XCSROM
87 -> - - - | - - - - | <-- 32MHZ
LC51 -> * - - | * * - - | <-- |9052rdfif:169|LMASTER
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\mev\live\1368\pld\1368_1.rpt
1368_1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------- LC44 ISA_INT
| +----- LC47 /RWE
| | +--- LC45 /SMEMR
| | | +- LC46 /SMEMW
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'C'
LC | | | | | A B C D | Logic cells that feed LAB 'C':
Pin
13 -> - - * - | - - * - | <-- /CS0
14 -> - - - * | - - * - | <-- /CS1
40 -> * - - - | - - * - | <-- IRQ2/9
41 -> * - - - | - - * - | <-- IRQ3
42 -> * - - - | - - * - | <-- IRQ4
44 -> * - - - | - - * - | <-- IRQ5
45 -> * - - - | - - * - | <-- IRQ6
46 -> * - - - | - - * - | <-- IRQ7
47 -> * - - - | - - * - | <-- IRQ10
48 -> * - - - | - - * - | <-- IRQ11
52 -> * - - - | - - * - | <-- IRQ12
54 -> * - - - | - - * - | <-- IRQ14
56 -> * - - - | - - * - | <-- IRQ15
16 -> - - * * | - - * - | <-- LA20
17 -> - - * * | - - * - | <-- LA21
19 -> - - * * | - - * - | <-- LA22
20 -> - - * * | - - * - | <-- LA23
90 -> - * - - | - - * - | <-- LCLK
88 -> - * - - | - - * - | <-- /WR
87 -> - - - - | - - - - | <-- 32MHZ
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\mev\live\1368\pld\1368_1.rpt
1368_1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------------------- LC49 PC8
| +--------------------------- LC50 PC9
| | +------------------------- LC52 PC10
| | | +----------------------- LC53 PC11
| | | | +--------------------- LC54 PC12
| | | | | +------------------- LC55 PC13
| | | | | | +----------------- LC57 PC14
| | | | | | | +--------------- LC58 PC15
| | | | | | | | +------------- LC59 PC16
| | | | | | | | | +----------- LC60 PC17
| | | | | | | | | | +--------- LC61 PC18
| | | | | | | | | | | +------- LC62 PC19
| | | | | | | | | | | | +----- LC63 PC20
| | | | | | | | | | | | | +--- LC64 PC21
| | | | | | | | | | | | | | +- LC51 |9052rdfif:169|LMASTER
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
Pin
90 -> - - - - - - - - - - - - - - - | - - * - | <-- LCLK
23 -> - - - - - - - - - - - - - - * | - - - * | <-- LHOLD
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